xref: /openbmc/u-boot/arch/x86/dts/minnowmax.dts (revision 8379c799)
1/*
2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
3 *
4 * SPDX-License-Identifier:	GPL-2.0+
5 */
6
7/dts-v1/;
8
9#include <dt-bindings/gpio/x86-gpio.h>
10
11/include/ "skeleton.dtsi"
12/include/ "serial.dtsi"
13
14/ {
15	model = "Intel Minnowboard Max";
16	compatible = "intel,minnowmax", "intel,baytrail";
17
18	aliases {
19		serial0 = &serial;
20		spi0 = "/spi";
21	};
22
23	config {
24		silent_console = <0>;
25	};
26
27	pch_pinctrl {
28		compatible = "intel,x86-pinctrl";
29		io-base = <0x4c>;
30
31		pin_usb_host_en0@0 {
32			gpio-offset = <0x80 8>;
33			pad-offset = <0x260>;
34			mode-gpio;
35			output-value = <1>;
36			direction = <PIN_OUTPUT>;
37		};
38
39		pin_usb_host_en1@0 {
40			gpio-offset = <0x80 9>;
41			pad-offset = <0x258>;
42			mode-gpio;
43			output-value = <1>;
44			direction = <PIN_OUTPUT>;
45		};
46	};
47
48	gpioa {
49		compatible = "intel,ich6-gpio";
50		u-boot,dm-pre-reloc;
51		reg = <0 0x20>;
52		bank-name = "A";
53	};
54
55	gpiob {
56		compatible = "intel,ich6-gpio";
57		u-boot,dm-pre-reloc;
58		reg = <0x20 0x20>;
59		bank-name = "B";
60	};
61
62	gpioc {
63		compatible = "intel,ich6-gpio";
64		u-boot,dm-pre-reloc;
65		reg = <0x40 0x20>;
66		bank-name = "C";
67	};
68
69	gpiod {
70		compatible = "intel,ich6-gpio";
71		u-boot,dm-pre-reloc;
72		reg = <0x60 0x20>;
73		bank-name = "D";
74	};
75
76	gpioe {
77		compatible = "intel,ich6-gpio";
78		u-boot,dm-pre-reloc;
79		reg = <0x80 0x20>;
80		bank-name = "E";
81	};
82
83	gpiof {
84		compatible = "intel,ich6-gpio";
85		u-boot,dm-pre-reloc;
86		reg = <0xA0 0x20>;
87		bank-name = "F";
88	};
89
90	chosen {
91		stdout-path = "/serial";
92	};
93
94	cpus {
95		#address-cells = <1>;
96		#size-cells = <0>;
97
98		cpu@0 {
99			device_type = "cpu";
100			compatible = "intel,baytrail-cpu";
101			reg = <0>;
102			intel,apic-id = <0>;
103		};
104
105		cpu@1 {
106			device_type = "cpu";
107			compatible = "intel,baytrail-cpu";
108			reg = <1>;
109			intel,apic-id = <4>;
110		};
111
112	};
113
114	spi {
115		#address-cells = <1>;
116		#size-cells = <0>;
117		compatible = "intel,ich-spi";
118		spi-flash@0 {
119			reg = <0>;
120			compatible = "stmicro,n25q064a", "spi-flash";
121			memory-map = <0xff800000 0x00800000>;
122		};
123	};
124
125	microcode {
126		update@0 {
127#include "microcode/m0130673322.dtsi"
128		};
129	};
130
131};
132