1/* 2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/gpio/x86-gpio.h> 10#include <dt-bindings/interrupt-router/intel-irq.h> 11 12/include/ "skeleton.dtsi" 13/include/ "serial.dtsi" 14/include/ "rtc.dtsi" 15/include/ "tsc_timer.dtsi" 16/include/ "coreboot_fb.dtsi" 17 18/ { 19 model = "Intel Minnowboard Max"; 20 compatible = "intel,minnowmax", "intel,baytrail"; 21 22 aliases { 23 serial0 = &serial; 24 spi0 = &spi; 25 }; 26 27 config { 28 silent_console = <0>; 29 }; 30 31 pch_pinctrl { 32 compatible = "intel,x86-pinctrl"; 33 reg = <0 0>; 34 35 /* GPIO E0 */ 36 soc_gpio_s5_0@0 { 37 gpio-offset = <0x80 0>; 38 pad-offset = <0x1d0>; 39 mode-gpio; 40 output-value = <0>; 41 direction = <PIN_OUTPUT>; 42 }; 43 44 /* GPIO E1 */ 45 soc_gpio_s5_1@0 { 46 gpio-offset = <0x80 1>; 47 pad-offset = <0x210>; 48 mode-gpio; 49 output-value = <0>; 50 direction = <PIN_OUTPUT>; 51 }; 52 53 /* GPIO E2 */ 54 soc_gpio_s5_2@0 { 55 gpio-offset = <0x80 2>; 56 pad-offset = <0x1e0>; 57 mode-gpio; 58 output-value = <0>; 59 direction = <PIN_OUTPUT>; 60 }; 61 62 pin_usb_host_en0@0 { 63 gpio-offset = <0x80 8>; 64 pad-offset = <0x260>; 65 mode-gpio; 66 output-value = <1>; 67 direction = <PIN_OUTPUT>; 68 }; 69 70 pin_usb_host_en1@0 { 71 gpio-offset = <0x80 9>; 72 pad-offset = <0x250>; 73 mode-gpio; 74 output-value = <1>; 75 direction = <PIN_OUTPUT>; 76 }; 77 78 /* 79 * As of today, the latest version FSP (gold4) for BayTrail 80 * misses the PAD configuration of the SD controller's Card 81 * Detect signal. The default PAD value for the CD pin sets 82 * the pin to work in GPIO mode, which causes card detect 83 * status cannot be reflected by the Present State register 84 * in the SD controller (bit 16 & bit 18 are always zero). 85 * 86 * Configure this pin to function 1 (SD controller). 87 */ 88 sdmmc3_cd@0 { 89 pad-offset = <0x3a0>; 90 mode-func = <1>; 91 }; 92 }; 93 94 chosen { 95 stdout-path = "/serial"; 96 }; 97 98 cpus { 99 #address-cells = <1>; 100 #size-cells = <0>; 101 102 cpu@0 { 103 device_type = "cpu"; 104 compatible = "intel,baytrail-cpu"; 105 reg = <0>; 106 intel,apic-id = <0>; 107 }; 108 109 cpu@1 { 110 device_type = "cpu"; 111 compatible = "intel,baytrail-cpu"; 112 reg = <1>; 113 intel,apic-id = <4>; 114 }; 115 116 }; 117 118 pci { 119 compatible = "intel,pci-baytrail", "pci-x86"; 120 #address-cells = <3>; 121 #size-cells = <2>; 122 u-boot,dm-pre-reloc; 123 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000 124 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 125 0x01000000 0x0 0x2000 0x2000 0 0xe000>; 126 127 pch@1f,0 { 128 reg = <0x0000f800 0 0 0 0>; 129 compatible = "pci8086,0f1c", "intel,pch9"; 130 #address-cells = <1>; 131 #size-cells = <1>; 132 133 irq-router { 134 compatible = "intel,irq-router"; 135 intel,pirq-config = "ibase"; 136 intel,ibase-offset = <0x50>; 137 intel,actl-addr = <0>; 138 intel,pirq-link = <8 8>; 139 intel,pirq-mask = <0xdee0>; 140 intel,pirq-routing = < 141 /* BayTrail PCI devices */ 142 PCI_BDF(0, 2, 0) INTA PIRQA 143 PCI_BDF(0, 3, 0) INTA PIRQA 144 PCI_BDF(0, 16, 0) INTA PIRQA 145 PCI_BDF(0, 17, 0) INTA PIRQA 146 PCI_BDF(0, 18, 0) INTA PIRQA 147 PCI_BDF(0, 19, 0) INTA PIRQA 148 PCI_BDF(0, 20, 0) INTA PIRQA 149 PCI_BDF(0, 21, 0) INTA PIRQA 150 PCI_BDF(0, 22, 0) INTA PIRQA 151 PCI_BDF(0, 23, 0) INTA PIRQA 152 PCI_BDF(0, 24, 0) INTA PIRQA 153 PCI_BDF(0, 24, 1) INTC PIRQC 154 PCI_BDF(0, 24, 2) INTD PIRQD 155 PCI_BDF(0, 24, 3) INTB PIRQB 156 PCI_BDF(0, 24, 4) INTA PIRQA 157 PCI_BDF(0, 24, 5) INTC PIRQC 158 PCI_BDF(0, 24, 6) INTD PIRQD 159 PCI_BDF(0, 24, 7) INTB PIRQB 160 PCI_BDF(0, 26, 0) INTA PIRQA 161 PCI_BDF(0, 27, 0) INTA PIRQA 162 PCI_BDF(0, 28, 0) INTA PIRQA 163 PCI_BDF(0, 28, 1) INTB PIRQB 164 PCI_BDF(0, 28, 2) INTC PIRQC 165 PCI_BDF(0, 28, 3) INTD PIRQD 166 PCI_BDF(0, 29, 0) INTA PIRQA 167 PCI_BDF(0, 30, 0) INTA PIRQA 168 PCI_BDF(0, 30, 1) INTD PIRQD 169 PCI_BDF(0, 30, 2) INTB PIRQB 170 PCI_BDF(0, 30, 3) INTC PIRQC 171 PCI_BDF(0, 30, 4) INTD PIRQD 172 PCI_BDF(0, 30, 5) INTB PIRQB 173 PCI_BDF(0, 31, 3) INTB PIRQB 174 175 /* 176 * PCIe root ports downstream 177 * interrupts 178 */ 179 PCI_BDF(1, 0, 0) INTA PIRQA 180 PCI_BDF(1, 0, 0) INTB PIRQB 181 PCI_BDF(1, 0, 0) INTC PIRQC 182 PCI_BDF(1, 0, 0) INTD PIRQD 183 PCI_BDF(2, 0, 0) INTA PIRQB 184 PCI_BDF(2, 0, 0) INTB PIRQC 185 PCI_BDF(2, 0, 0) INTC PIRQD 186 PCI_BDF(2, 0, 0) INTD PIRQA 187 PCI_BDF(3, 0, 0) INTA PIRQC 188 PCI_BDF(3, 0, 0) INTB PIRQD 189 PCI_BDF(3, 0, 0) INTC PIRQA 190 PCI_BDF(3, 0, 0) INTD PIRQB 191 PCI_BDF(4, 0, 0) INTA PIRQD 192 PCI_BDF(4, 0, 0) INTB PIRQA 193 PCI_BDF(4, 0, 0) INTC PIRQB 194 PCI_BDF(4, 0, 0) INTD PIRQC 195 >; 196 }; 197 198 spi: spi { 199 #address-cells = <1>; 200 #size-cells = <0>; 201 compatible = "intel,ich9-spi"; 202 spi-flash@0 { 203 #address-cells = <1>; 204 #size-cells = <1>; 205 reg = <0>; 206 compatible = "stmicro,n25q064a", 207 "spi-flash"; 208 memory-map = <0xff800000 0x00800000>; 209 rw-mrc-cache { 210 label = "rw-mrc-cache"; 211 reg = <0x006f0000 0x00010000>; 212 }; 213 }; 214 }; 215 216 gpioa { 217 compatible = "intel,ich6-gpio"; 218 u-boot,dm-pre-reloc; 219 reg = <0 0x20>; 220 bank-name = "A"; 221 }; 222 223 gpiob { 224 compatible = "intel,ich6-gpio"; 225 u-boot,dm-pre-reloc; 226 reg = <0x20 0x20>; 227 bank-name = "B"; 228 }; 229 230 gpioc { 231 compatible = "intel,ich6-gpio"; 232 u-boot,dm-pre-reloc; 233 reg = <0x40 0x20>; 234 bank-name = "C"; 235 }; 236 237 gpiod { 238 compatible = "intel,ich6-gpio"; 239 u-boot,dm-pre-reloc; 240 reg = <0x60 0x20>; 241 bank-name = "D"; 242 }; 243 244 gpioe { 245 compatible = "intel,ich6-gpio"; 246 u-boot,dm-pre-reloc; 247 reg = <0x80 0x20>; 248 bank-name = "E"; 249 }; 250 251 gpiof { 252 compatible = "intel,ich6-gpio"; 253 u-boot,dm-pre-reloc; 254 reg = <0xA0 0x20>; 255 bank-name = "F"; 256 }; 257 }; 258 }; 259 260 fsp { 261 compatible = "intel,baytrail-fsp"; 262 fsp,mrc-init-tseg-size = <0>; 263 fsp,mrc-init-mmio-size = <0x800>; 264 fsp,mrc-init-spd-addr1 = <0xa0>; 265 fsp,mrc-init-spd-addr2 = <0xa2>; 266 fsp,emmc-boot-mode = <1>; 267 fsp,enable-sdio; 268 fsp,enable-sdcard; 269 fsp,enable-hsuart1; 270 fsp,enable-spi; 271 fsp,enable-sata; 272 fsp,sata-mode = <1>; 273 fsp,enable-lpe; 274 fsp,lpss-sio-enable-pci-mode; 275 fsp,enable-dma0; 276 fsp,enable-dma1; 277 fsp,enable-i2c0; 278 fsp,enable-i2c1; 279 fsp,enable-i2c2; 280 fsp,enable-i2c3; 281 fsp,enable-i2c4; 282 fsp,enable-i2c5; 283 fsp,enable-i2c6; 284 fsp,enable-pwm0; 285 fsp,enable-pwm1; 286 fsp,igd-dvmt50-pre-alloc = <2>; 287 fsp,aperture-size = <2>; 288 fsp,gtt-size = <2>; 289 fsp,serial-debug-port-address = <0x3f8>; 290 fsp,serial-debug-port-type = <1>; 291 fsp,scc-enable-pci-mode; 292 fsp,os-selection = <4>; 293 fsp,emmc45-ddr50-enabled; 294 fsp,emmc45-retune-timer-value = <8>; 295 fsp,enable-igd; 296 fsp,enable-memory-down; 297 fsp,memory-down-params { 298 compatible = "intel,baytrail-fsp-mdp"; 299 fsp,dram-speed = <1>; 300 fsp,dram-type = <1>; 301 fsp,dimm-0-enable; 302 fsp,dimm-width = <1>; 303 fsp,dimm-density = <2>; 304 fsp,dimm-bus-width = <3>; 305 fsp,dimm-sides = <0>; 306 fsp,dimm-tcl = <0xb>; 307 fsp,dimm-trpt-rcd = <0xb>; 308 fsp,dimm-twr = <0xc>; 309 fsp,dimm-twtr = <6>; 310 fsp,dimm-trrd = <6>; 311 fsp,dimm-trtp = <6>; 312 fsp,dimm-tfaw = <0x14>; 313 }; 314 }; 315 316 microcode { 317 update@0 { 318#include "microcode/m0130673325.dtsi" 319 }; 320 update@1 { 321#include "microcode/m0130679907.dtsi" 322 }; 323 }; 324 325}; 326