1fa87abb6SPatrice Chotard /*
2fa87abb6SPatrice Chotard  * This header provides constants for the STM32F7 RCC IP
3fa87abb6SPatrice Chotard  */
4fa87abb6SPatrice Chotard 
5fa87abb6SPatrice Chotard #ifndef _DT_BINDINGS_MFD_STM32F7_RCC_H
6fa87abb6SPatrice Chotard #define _DT_BINDINGS_MFD_STM32F7_RCC_H
7fa87abb6SPatrice Chotard 
8fa87abb6SPatrice Chotard /* AHB1 */
9fa87abb6SPatrice Chotard #define STM32F7_RCC_AHB1_GPIOA		0
10fa87abb6SPatrice Chotard #define STM32F7_RCC_AHB1_GPIOB		1
11fa87abb6SPatrice Chotard #define STM32F7_RCC_AHB1_GPIOC		2
12fa87abb6SPatrice Chotard #define STM32F7_RCC_AHB1_GPIOD		3
13fa87abb6SPatrice Chotard #define STM32F7_RCC_AHB1_GPIOE		4
14fa87abb6SPatrice Chotard #define STM32F7_RCC_AHB1_GPIOF		5
15fa87abb6SPatrice Chotard #define STM32F7_RCC_AHB1_GPIOG		6
16fa87abb6SPatrice Chotard #define STM32F7_RCC_AHB1_GPIOH		7
17fa87abb6SPatrice Chotard #define STM32F7_RCC_AHB1_GPIOI		8
18fa87abb6SPatrice Chotard #define STM32F7_RCC_AHB1_GPIOJ		9
19fa87abb6SPatrice Chotard #define STM32F7_RCC_AHB1_GPIOK		10
20fa87abb6SPatrice Chotard #define STM32F7_RCC_AHB1_CRC		12
21fa87abb6SPatrice Chotard #define STM32F7_RCC_AHB1_BKPSRAM	18
22fa87abb6SPatrice Chotard #define STM32F7_RCC_AHB1_DTCMRAM	20
23fa87abb6SPatrice Chotard #define STM32F7_RCC_AHB1_DMA1		21
24fa87abb6SPatrice Chotard #define STM32F7_RCC_AHB1_DMA2		22
25fa87abb6SPatrice Chotard #define STM32F7_RCC_AHB1_DMA2D		23
26fa87abb6SPatrice Chotard #define STM32F7_RCC_AHB1_ETHMAC		25
27fa87abb6SPatrice Chotard #define STM32F7_RCC_AHB1_ETHMACTX	26
28fa87abb6SPatrice Chotard #define STM32F7_RCC_AHB1_ETHMACRX	27
29fa87abb6SPatrice Chotard #define STM32FF_RCC_AHB1_ETHMACPTP	28
30fa87abb6SPatrice Chotard #define STM32F7_RCC_AHB1_OTGHS		29
31fa87abb6SPatrice Chotard #define STM32F7_RCC_AHB1_OTGHSULPI	30
32fa87abb6SPatrice Chotard 
33fa87abb6SPatrice Chotard #define STM32F7_AHB1_RESET(bit) (STM32F7_RCC_AHB1_##bit + (0x10 * 8))
34fa87abb6SPatrice Chotard #define STM32F7_AHB1_CLOCK(bit) (STM32F7_RCC_AHB1_##bit)
35fa87abb6SPatrice Chotard 
36fa87abb6SPatrice Chotard 
37fa87abb6SPatrice Chotard /* AHB2 */
38fa87abb6SPatrice Chotard #define STM32F7_RCC_AHB2_DCMI		0
39fa87abb6SPatrice Chotard #define STM32F7_RCC_AHB2_CRYP		4
40fa87abb6SPatrice Chotard #define STM32F7_RCC_AHB2_HASH		5
41fa87abb6SPatrice Chotard #define STM32F7_RCC_AHB2_RNG		6
42fa87abb6SPatrice Chotard #define STM32F7_RCC_AHB2_OTGFS		7
43fa87abb6SPatrice Chotard 
44fa87abb6SPatrice Chotard #define STM32F7_AHB2_RESET(bit)	(STM32F7_RCC_AHB2_##bit + (0x14 * 8))
45fa87abb6SPatrice Chotard #define STM32F7_AHB2_CLOCK(bit)	(STM32F7_RCC_AHB2_##bit + 0x20)
46fa87abb6SPatrice Chotard 
47fa87abb6SPatrice Chotard /* AHB3 */
48fa87abb6SPatrice Chotard #define STM32F7_RCC_AHB3_FMC		0
49fa87abb6SPatrice Chotard #define STM32F7_RCC_AHB3_QSPI		1
50fa87abb6SPatrice Chotard 
51fa87abb6SPatrice Chotard #define STM32F7_AHB3_RESET(bit)	(STM32F7_RCC_AHB3_##bit + (0x18 * 8))
52fa87abb6SPatrice Chotard #define STM32F7_AHB3_CLOCK(bit)	(STM32F7_RCC_AHB3_##bit + 0x40)
53fa87abb6SPatrice Chotard 
54fa87abb6SPatrice Chotard /* APB1 */
55fa87abb6SPatrice Chotard #define STM32F7_RCC_APB1_TIM2		0
56fa87abb6SPatrice Chotard #define STM32F7_RCC_APB1_TIM3		1
57fa87abb6SPatrice Chotard #define STM32F7_RCC_APB1_TIM4		2
58fa87abb6SPatrice Chotard #define STM32F7_RCC_APB1_TIM5		3
59fa87abb6SPatrice Chotard #define STM32F7_RCC_APB1_TIM6		4
60fa87abb6SPatrice Chotard #define STM32F7_RCC_APB1_TIM7		5
61fa87abb6SPatrice Chotard #define STM32F7_RCC_APB1_TIM12		6
62fa87abb6SPatrice Chotard #define STM32F7_RCC_APB1_TIM13		7
63fa87abb6SPatrice Chotard #define STM32F7_RCC_APB1_TIM14		8
64fa87abb6SPatrice Chotard #define STM32F7_RCC_APB1_LPTIM1		9
65fa87abb6SPatrice Chotard #define STM32F7_RCC_APB1_WWDG		11
66fa87abb6SPatrice Chotard #define STM32F7_RCC_APB1_SPI2		14
67fa87abb6SPatrice Chotard #define STM32F7_RCC_APB1_SPI3		15
68fa87abb6SPatrice Chotard #define STM32F7_RCC_APB1_SPDIFRX	16
69fa87abb6SPatrice Chotard #define STM32F7_RCC_APB1_UART2		17
70fa87abb6SPatrice Chotard #define STM32F7_RCC_APB1_UART3		18
71fa87abb6SPatrice Chotard #define STM32F7_RCC_APB1_UART4		19
72fa87abb6SPatrice Chotard #define STM32F7_RCC_APB1_UART5		20
73fa87abb6SPatrice Chotard #define STM32F7_RCC_APB1_I2C1		21
74fa87abb6SPatrice Chotard #define STM32F7_RCC_APB1_I2C2		22
75fa87abb6SPatrice Chotard #define STM32F7_RCC_APB1_I2C3		23
76fa87abb6SPatrice Chotard #define STM32F7_RCC_APB1_I2C4		24
77fa87abb6SPatrice Chotard #define STM32F7_RCC_APB1_CAN1		25
78fa87abb6SPatrice Chotard #define STM32F7_RCC_APB1_CAN2		26
79fa87abb6SPatrice Chotard #define STM32F7_RCC_APB1_CEC		27
80fa87abb6SPatrice Chotard #define STM32F7_RCC_APB1_PWR		28
81fa87abb6SPatrice Chotard #define STM32F7_RCC_APB1_DAC		29
82fa87abb6SPatrice Chotard #define STM32F7_RCC_APB1_UART7		30
83fa87abb6SPatrice Chotard #define STM32F7_RCC_APB1_UART8		31
84fa87abb6SPatrice Chotard 
85fa87abb6SPatrice Chotard #define STM32F7_APB1_RESET(bit)	(STM32F7_RCC_APB1_##bit + (0x20 * 8))
86fa87abb6SPatrice Chotard #define STM32F7_APB1_CLOCK(bit)	(STM32F7_RCC_APB1_##bit + 0x80)
87fa87abb6SPatrice Chotard 
88fa87abb6SPatrice Chotard /* APB2 */
89fa87abb6SPatrice Chotard #define STM32F7_RCC_APB2_TIM1		0
90fa87abb6SPatrice Chotard #define STM32F7_RCC_APB2_TIM8		1
91fa87abb6SPatrice Chotard #define STM32F7_RCC_APB2_USART1		4
92fa87abb6SPatrice Chotard #define STM32F7_RCC_APB2_USART6		5
934e97e257SPatrice Chotard #define STM32F7_RCC_APB2_SDMMC2		7
94fa87abb6SPatrice Chotard #define STM32F7_RCC_APB2_ADC1		8
95fa87abb6SPatrice Chotard #define STM32F7_RCC_APB2_ADC2		9
96fa87abb6SPatrice Chotard #define STM32F7_RCC_APB2_ADC3		10
97fa87abb6SPatrice Chotard #define STM32F7_RCC_APB2_SDMMC1		11
98fa87abb6SPatrice Chotard #define STM32F7_RCC_APB2_SPI1		12
99fa87abb6SPatrice Chotard #define STM32F7_RCC_APB2_SPI4		13
100fa87abb6SPatrice Chotard #define STM32F7_RCC_APB2_SYSCFG		14
101fa87abb6SPatrice Chotard #define STM32F7_RCC_APB2_TIM9		16
102fa87abb6SPatrice Chotard #define STM32F7_RCC_APB2_TIM10		17
103fa87abb6SPatrice Chotard #define STM32F7_RCC_APB2_TIM11		18
104fa87abb6SPatrice Chotard #define STM32F7_RCC_APB2_SPI5		20
105fa87abb6SPatrice Chotard #define STM32F7_RCC_APB2_SPI6		21
106fa87abb6SPatrice Chotard #define STM32F7_RCC_APB2_SAI1		22
107fa87abb6SPatrice Chotard #define STM32F7_RCC_APB2_SAI2		23
108fa87abb6SPatrice Chotard #define STM32F7_RCC_APB2_LTDC		26
109*6243c884SPatrice Chotard #define STM32F7_RCC_APB2_DSI		27
110fa87abb6SPatrice Chotard 
111fa87abb6SPatrice Chotard #define STM32F7_APB2_RESET(bit)	(STM32F7_RCC_APB2_##bit + (0x24 * 8))
112fa87abb6SPatrice Chotard #define STM32F7_APB2_CLOCK(bit)	(STM32F7_RCC_APB2_##bit + 0xA0)
113fa87abb6SPatrice Chotard 
114fa87abb6SPatrice Chotard #endif /* _DT_BINDINGS_MFD_STM32F7_RCC_H */
115