1c3691392SSimon Glass /* 2c3691392SSimon Glass * This header provides constants for binding nvidia,tegra30-car. 3c3691392SSimon Glass * 4c3691392SSimon Glass * The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB 5c3691392SSimon Glass * registers. These IDs often match those in the CAR's RST_DEVICES registers, 6c3691392SSimon Glass * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In 7c3691392SSimon Glass * this case, those clocks are assigned IDs above 160 in order to highlight 8c3691392SSimon Glass * this issue. Implementations that interpret these clock IDs as bit values 9c3691392SSimon Glass * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to 10c3691392SSimon Glass * explicitly handle these special cases. 11c3691392SSimon Glass * 12c3691392SSimon Glass * The balance of the clocks controlled by the CAR are assigned IDs of 160 and 13c3691392SSimon Glass * above. 14c3691392SSimon Glass */ 15c3691392SSimon Glass 16c3691392SSimon Glass #ifndef _DT_BINDINGS_CLOCK_TEGRA30_CAR_H 17c3691392SSimon Glass #define _DT_BINDINGS_CLOCK_TEGRA30_CAR_H 18c3691392SSimon Glass 19c3691392SSimon Glass #define TEGRA30_CLK_CPU 0 20c3691392SSimon Glass /* 1 */ 21c3691392SSimon Glass /* 2 */ 22c3691392SSimon Glass /* 3 */ 23c3691392SSimon Glass #define TEGRA30_CLK_RTC 4 24c3691392SSimon Glass #define TEGRA30_CLK_TIMER 5 25c3691392SSimon Glass #define TEGRA30_CLK_UARTA 6 26c3691392SSimon Glass /* 7 (register bit affects uartb and vfir) */ 27c3691392SSimon Glass #define TEGRA30_CLK_GPIO 8 28c3691392SSimon Glass #define TEGRA30_CLK_SDMMC2 9 29c3691392SSimon Glass /* 10 (register bit affects spdif_in and spdif_out) */ 30c3691392SSimon Glass #define TEGRA30_CLK_I2S1 11 31c3691392SSimon Glass #define TEGRA30_CLK_I2C1 12 32c3691392SSimon Glass #define TEGRA30_CLK_NDFLASH 13 33c3691392SSimon Glass #define TEGRA30_CLK_SDMMC1 14 34c3691392SSimon Glass #define TEGRA30_CLK_SDMMC4 15 35c3691392SSimon Glass /* 16 */ 36c3691392SSimon Glass #define TEGRA30_CLK_PWM 17 37c3691392SSimon Glass #define TEGRA30_CLK_I2S2 18 38c3691392SSimon Glass #define TEGRA30_CLK_EPP 19 39c3691392SSimon Glass /* 20 (register bit affects vi and vi_sensor) */ 40c3691392SSimon Glass #define TEGRA30_CLK_GR2D 21 41c3691392SSimon Glass #define TEGRA30_CLK_USBD 22 42c3691392SSimon Glass #define TEGRA30_CLK_ISP 23 43c3691392SSimon Glass #define TEGRA30_CLK_GR3D 24 44c3691392SSimon Glass /* 25 */ 45c3691392SSimon Glass #define TEGRA30_CLK_DISP2 26 46c3691392SSimon Glass #define TEGRA30_CLK_DISP1 27 47c3691392SSimon Glass #define TEGRA30_CLK_HOST1X 28 48c3691392SSimon Glass #define TEGRA30_CLK_VCP 29 49c3691392SSimon Glass #define TEGRA30_CLK_I2S0 30 50c3691392SSimon Glass #define TEGRA30_CLK_COP_CACHE 31 51c3691392SSimon Glass 52c3691392SSimon Glass #define TEGRA30_CLK_MC 32 53c3691392SSimon Glass #define TEGRA30_CLK_AHBDMA 33 54c3691392SSimon Glass #define TEGRA30_CLK_APBDMA 34 55c3691392SSimon Glass /* 35 */ 56c3691392SSimon Glass #define TEGRA30_CLK_KBC 36 57c3691392SSimon Glass #define TEGRA30_CLK_STATMON 37 58c3691392SSimon Glass #define TEGRA30_CLK_PMC 38 59c3691392SSimon Glass /* 39 (register bit affects fuse and fuse_burn) */ 60c3691392SSimon Glass #define TEGRA30_CLK_KFUSE 40 61c3691392SSimon Glass #define TEGRA30_CLK_SBC1 41 62c3691392SSimon Glass #define TEGRA30_CLK_NOR 42 63c3691392SSimon Glass /* 43 */ 64c3691392SSimon Glass #define TEGRA30_CLK_SBC2 44 65c3691392SSimon Glass /* 45 */ 66c3691392SSimon Glass #define TEGRA30_CLK_SBC3 46 67c3691392SSimon Glass #define TEGRA30_CLK_I2C5 47 68c3691392SSimon Glass #define TEGRA30_CLK_DSIA 48 69c3691392SSimon Glass /* 49 (register bit affects cve and tvo) */ 70c3691392SSimon Glass #define TEGRA30_CLK_MIPI 50 71c3691392SSimon Glass #define TEGRA30_CLK_HDMI 51 72c3691392SSimon Glass #define TEGRA30_CLK_CSI 52 73c3691392SSimon Glass #define TEGRA30_CLK_TVDAC 53 74c3691392SSimon Glass #define TEGRA30_CLK_I2C2 54 75c3691392SSimon Glass #define TEGRA30_CLK_UARTC 55 76c3691392SSimon Glass /* 56 */ 77c3691392SSimon Glass #define TEGRA30_CLK_EMC 57 78c3691392SSimon Glass #define TEGRA30_CLK_USB2 58 79c3691392SSimon Glass #define TEGRA30_CLK_USB3 59 80c3691392SSimon Glass #define TEGRA30_CLK_MPE 60 81c3691392SSimon Glass #define TEGRA30_CLK_VDE 61 82c3691392SSimon Glass #define TEGRA30_CLK_BSEA 62 83c3691392SSimon Glass #define TEGRA30_CLK_BSEV 63 84c3691392SSimon Glass 85c3691392SSimon Glass #define TEGRA30_CLK_SPEEDO 64 86c3691392SSimon Glass #define TEGRA30_CLK_UARTD 65 87c3691392SSimon Glass #define TEGRA30_CLK_UARTE 66 88c3691392SSimon Glass #define TEGRA30_CLK_I2C3 67 89c3691392SSimon Glass #define TEGRA30_CLK_SBC4 68 90c3691392SSimon Glass #define TEGRA30_CLK_SDMMC3 69 91c3691392SSimon Glass #define TEGRA30_CLK_PCIE 70 92c3691392SSimon Glass #define TEGRA30_CLK_OWR 71 93c3691392SSimon Glass #define TEGRA30_CLK_AFI 72 94c3691392SSimon Glass #define TEGRA30_CLK_CSITE 73 95*ce2f2d2aSStephen Warren /* 74 */ 96c3691392SSimon Glass #define TEGRA30_CLK_AVPUCQ 75 97c3691392SSimon Glass #define TEGRA30_CLK_LA 76 98c3691392SSimon Glass /* 77 */ 99c3691392SSimon Glass /* 78 */ 100c3691392SSimon Glass #define TEGRA30_CLK_DTV 79 101c3691392SSimon Glass #define TEGRA30_CLK_NDSPEED 80 102c3691392SSimon Glass #define TEGRA30_CLK_I2CSLOW 81 103c3691392SSimon Glass #define TEGRA30_CLK_DSIB 82 104c3691392SSimon Glass /* 83 */ 105c3691392SSimon Glass #define TEGRA30_CLK_IRAMA 84 106c3691392SSimon Glass #define TEGRA30_CLK_IRAMB 85 107c3691392SSimon Glass #define TEGRA30_CLK_IRAMC 86 108c3691392SSimon Glass #define TEGRA30_CLK_IRAMD 87 109c3691392SSimon Glass #define TEGRA30_CLK_CRAM2 88 110c3691392SSimon Glass /* 89 */ 111c3691392SSimon Glass #define TEGRA30_CLK_AUDIO_2X 90 /* a/k/a audio_2x_sync_clk */ 112c3691392SSimon Glass /* 91 */ 113c3691392SSimon Glass #define TEGRA30_CLK_CSUS 92 114c3691392SSimon Glass #define TEGRA30_CLK_CDEV2 93 115c3691392SSimon Glass #define TEGRA30_CLK_CDEV1 94 116c3691392SSimon Glass /* 95 */ 117c3691392SSimon Glass 118c3691392SSimon Glass #define TEGRA30_CLK_CPU_G 96 119c3691392SSimon Glass #define TEGRA30_CLK_CPU_LP 97 120c3691392SSimon Glass #define TEGRA30_CLK_GR3D2 98 121c3691392SSimon Glass #define TEGRA30_CLK_MSELECT 99 122c3691392SSimon Glass #define TEGRA30_CLK_TSENSOR 100 123c3691392SSimon Glass #define TEGRA30_CLK_I2S3 101 124c3691392SSimon Glass #define TEGRA30_CLK_I2S4 102 125c3691392SSimon Glass #define TEGRA30_CLK_I2C4 103 126c3691392SSimon Glass #define TEGRA30_CLK_SBC5 104 127c3691392SSimon Glass #define TEGRA30_CLK_SBC6 105 128c3691392SSimon Glass #define TEGRA30_CLK_D_AUDIO 106 129c3691392SSimon Glass #define TEGRA30_CLK_APBIF 107 130c3691392SSimon Glass #define TEGRA30_CLK_DAM0 108 131c3691392SSimon Glass #define TEGRA30_CLK_DAM1 109 132c3691392SSimon Glass #define TEGRA30_CLK_DAM2 110 133c3691392SSimon Glass #define TEGRA30_CLK_HDA2CODEC_2X 111 134c3691392SSimon Glass #define TEGRA30_CLK_ATOMICS 112 135c3691392SSimon Glass #define TEGRA30_CLK_AUDIO0_2X 113 136c3691392SSimon Glass #define TEGRA30_CLK_AUDIO1_2X 114 137c3691392SSimon Glass #define TEGRA30_CLK_AUDIO2_2X 115 138c3691392SSimon Glass #define TEGRA30_CLK_AUDIO3_2X 116 139c3691392SSimon Glass #define TEGRA30_CLK_AUDIO4_2X 117 140c3691392SSimon Glass #define TEGRA30_CLK_SPDIF_2X 118 141c3691392SSimon Glass #define TEGRA30_CLK_ACTMON 119 142c3691392SSimon Glass #define TEGRA30_CLK_EXTERN1 120 143c3691392SSimon Glass #define TEGRA30_CLK_EXTERN2 121 144c3691392SSimon Glass #define TEGRA30_CLK_EXTERN3 122 145c3691392SSimon Glass #define TEGRA30_CLK_SATA_OOB 123 146c3691392SSimon Glass #define TEGRA30_CLK_SATA 124 147c3691392SSimon Glass #define TEGRA30_CLK_HDA 125 148c3691392SSimon Glass /* 126 */ 149c3691392SSimon Glass #define TEGRA30_CLK_SE 127 150c3691392SSimon Glass 151c3691392SSimon Glass #define TEGRA30_CLK_HDA2HDMI 128 152c3691392SSimon Glass #define TEGRA30_CLK_SATA_COLD 129 153c3691392SSimon Glass /* 130 */ 154c3691392SSimon Glass /* 131 */ 155c3691392SSimon Glass /* 132 */ 156c3691392SSimon Glass /* 133 */ 157c3691392SSimon Glass /* 134 */ 158c3691392SSimon Glass /* 135 */ 159c3691392SSimon Glass /* 136 */ 160c3691392SSimon Glass /* 137 */ 161c3691392SSimon Glass /* 138 */ 162c3691392SSimon Glass /* 139 */ 163c3691392SSimon Glass /* 140 */ 164c3691392SSimon Glass /* 141 */ 165c3691392SSimon Glass /* 142 */ 166c3691392SSimon Glass /* 143 */ 167c3691392SSimon Glass /* 144 */ 168c3691392SSimon Glass /* 145 */ 169c3691392SSimon Glass /* 146 */ 170c3691392SSimon Glass /* 147 */ 171c3691392SSimon Glass /* 148 */ 172c3691392SSimon Glass /* 149 */ 173c3691392SSimon Glass /* 150 */ 174c3691392SSimon Glass /* 151 */ 175c3691392SSimon Glass /* 152 */ 176c3691392SSimon Glass /* 153 */ 177c3691392SSimon Glass /* 154 */ 178c3691392SSimon Glass /* 155 */ 179c3691392SSimon Glass /* 156 */ 180c3691392SSimon Glass /* 157 */ 181c3691392SSimon Glass /* 158 */ 182c3691392SSimon Glass /* 159 */ 183c3691392SSimon Glass 184c3691392SSimon Glass #define TEGRA30_CLK_UARTB 160 185c3691392SSimon Glass #define TEGRA30_CLK_VFIR 161 186c3691392SSimon Glass #define TEGRA30_CLK_SPDIF_IN 162 187c3691392SSimon Glass #define TEGRA30_CLK_SPDIF_OUT 163 188c3691392SSimon Glass #define TEGRA30_CLK_VI 164 189c3691392SSimon Glass #define TEGRA30_CLK_VI_SENSOR 165 190c3691392SSimon Glass #define TEGRA30_CLK_FUSE 166 191c3691392SSimon Glass #define TEGRA30_CLK_FUSE_BURN 167 192c3691392SSimon Glass #define TEGRA30_CLK_CVE 168 193c3691392SSimon Glass #define TEGRA30_CLK_TVO 169 194c3691392SSimon Glass #define TEGRA30_CLK_CLK_32K 170 195c3691392SSimon Glass #define TEGRA30_CLK_CLK_M 171 196c3691392SSimon Glass #define TEGRA30_CLK_CLK_M_DIV2 172 197c3691392SSimon Glass #define TEGRA30_CLK_CLK_M_DIV4 173 198c3691392SSimon Glass #define TEGRA30_CLK_PLL_REF 174 199c3691392SSimon Glass #define TEGRA30_CLK_PLL_C 175 200c3691392SSimon Glass #define TEGRA30_CLK_PLL_C_OUT1 176 201c3691392SSimon Glass #define TEGRA30_CLK_PLL_M 177 202c3691392SSimon Glass #define TEGRA30_CLK_PLL_M_OUT1 178 203c3691392SSimon Glass #define TEGRA30_CLK_PLL_P 179 204c3691392SSimon Glass #define TEGRA30_CLK_PLL_P_OUT1 180 205c3691392SSimon Glass #define TEGRA30_CLK_PLL_P_OUT2 181 206c3691392SSimon Glass #define TEGRA30_CLK_PLL_P_OUT3 182 207c3691392SSimon Glass #define TEGRA30_CLK_PLL_P_OUT4 183 208c3691392SSimon Glass #define TEGRA30_CLK_PLL_A 184 209c3691392SSimon Glass #define TEGRA30_CLK_PLL_A_OUT0 185 210c3691392SSimon Glass #define TEGRA30_CLK_PLL_D 186 211c3691392SSimon Glass #define TEGRA30_CLK_PLL_D_OUT0 187 212c3691392SSimon Glass #define TEGRA30_CLK_PLL_D2 188 213c3691392SSimon Glass #define TEGRA30_CLK_PLL_D2_OUT0 189 214c3691392SSimon Glass #define TEGRA30_CLK_PLL_U 190 215c3691392SSimon Glass #define TEGRA30_CLK_PLL_X 191 216c3691392SSimon Glass 217c3691392SSimon Glass #define TEGRA30_CLK_PLL_X_OUT0 192 218c3691392SSimon Glass #define TEGRA30_CLK_PLL_E 193 219c3691392SSimon Glass #define TEGRA30_CLK_SPDIF_IN_SYNC 194 220c3691392SSimon Glass #define TEGRA30_CLK_I2S0_SYNC 195 221c3691392SSimon Glass #define TEGRA30_CLK_I2S1_SYNC 196 222c3691392SSimon Glass #define TEGRA30_CLK_I2S2_SYNC 197 223c3691392SSimon Glass #define TEGRA30_CLK_I2S3_SYNC 198 224c3691392SSimon Glass #define TEGRA30_CLK_I2S4_SYNC 199 225c3691392SSimon Glass #define TEGRA30_CLK_VIMCLK_SYNC 200 226c3691392SSimon Glass #define TEGRA30_CLK_AUDIO0 201 227c3691392SSimon Glass #define TEGRA30_CLK_AUDIO1 202 228c3691392SSimon Glass #define TEGRA30_CLK_AUDIO2 203 229c3691392SSimon Glass #define TEGRA30_CLK_AUDIO3 204 230c3691392SSimon Glass #define TEGRA30_CLK_AUDIO4 205 231c3691392SSimon Glass #define TEGRA30_CLK_SPDIF 206 232c3691392SSimon Glass #define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */ 233c3691392SSimon Glass #define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */ 234c3691392SSimon Glass #define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */ 235c3691392SSimon Glass #define TEGRA30_CLK_SCLK 210 236c3691392SSimon Glass #define TEGRA30_CLK_BLINK 211 237c3691392SSimon Glass #define TEGRA30_CLK_CCLK_G 212 238c3691392SSimon Glass #define TEGRA30_CLK_CCLK_LP 213 239c3691392SSimon Glass #define TEGRA30_CLK_TWD 214 240c3691392SSimon Glass #define TEGRA30_CLK_CML0 215 241c3691392SSimon Glass #define TEGRA30_CLK_CML1 216 242c3691392SSimon Glass #define TEGRA30_CLK_HCLK 217 243c3691392SSimon Glass #define TEGRA30_CLK_PCLK 218 244c3691392SSimon Glass /* 219 */ 245c3691392SSimon Glass /* 220 */ 246c3691392SSimon Glass /* 221 */ 247c3691392SSimon Glass /* 222 */ 248c3691392SSimon Glass /* 223 */ 249c3691392SSimon Glass 250c3691392SSimon Glass /* 288 */ 251c3691392SSimon Glass /* 289 */ 252c3691392SSimon Glass /* 290 */ 253c3691392SSimon Glass /* 291 */ 254c3691392SSimon Glass /* 292 */ 255c3691392SSimon Glass /* 293 */ 256c3691392SSimon Glass /* 294 */ 257c3691392SSimon Glass /* 295 */ 258c3691392SSimon Glass /* 296 */ 259c3691392SSimon Glass /* 297 */ 260c3691392SSimon Glass /* 298 */ 261c3691392SSimon Glass /* 299 */ 262c3691392SSimon Glass #define TEGRA30_CLK_CLK_OUT_1_MUX 300 263c3691392SSimon Glass #define TEGRA30_CLK_CLK_OUT_2_MUX 301 264c3691392SSimon Glass #define TEGRA30_CLK_CLK_OUT_3_MUX 302 265c3691392SSimon Glass #define TEGRA30_CLK_AUDIO0_MUX 303 266c3691392SSimon Glass #define TEGRA30_CLK_AUDIO1_MUX 304 267c3691392SSimon Glass #define TEGRA30_CLK_AUDIO2_MUX 305 268c3691392SSimon Glass #define TEGRA30_CLK_AUDIO3_MUX 306 269c3691392SSimon Glass #define TEGRA30_CLK_AUDIO4_MUX 307 270c3691392SSimon Glass #define TEGRA30_CLK_SPDIF_MUX 308 271c3691392SSimon Glass #define TEGRA30_CLK_CLK_MAX 309 272c3691392SSimon Glass 273c3691392SSimon Glass #endif /* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */ 274