1e80dac0aSEugeniy Paltsev /* 2e80dac0aSEugeniy Paltsev * Synopsys HSDK SDP CGU clock driver dts bindings 3e80dac0aSEugeniy Paltsev * 4e80dac0aSEugeniy Paltsev * Copyright (C) 2017 Synopsys 5e80dac0aSEugeniy Paltsev * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> 6e80dac0aSEugeniy Paltsev * 7e80dac0aSEugeniy Paltsev * This file is licensed under the terms of the GNU General Public 8e80dac0aSEugeniy Paltsev * License version 2. This program is licensed "as is" without any 9e80dac0aSEugeniy Paltsev * warranty of any kind, whether express or implied. 10e80dac0aSEugeniy Paltsev */ 11e80dac0aSEugeniy Paltsev 12e80dac0aSEugeniy Paltsev #ifndef __DT_BINDINGS_CLK_HSDK_CGU_H_ 13e80dac0aSEugeniy Paltsev #define __DT_BINDINGS_CLK_HSDK_CGU_H_ 14e80dac0aSEugeniy Paltsev 15e80dac0aSEugeniy Paltsev #define CLK_ARC_PLL 0 16e80dac0aSEugeniy Paltsev #define CLK_ARC 1 17e80dac0aSEugeniy Paltsev #define CLK_DDR_PLL 2 18e80dac0aSEugeniy Paltsev #define CLK_SYS_PLL 3 19e80dac0aSEugeniy Paltsev #define CLK_SYS_APB 4 20e80dac0aSEugeniy Paltsev #define CLK_SYS_AXI 5 21e80dac0aSEugeniy Paltsev #define CLK_SYS_ETH 6 22e80dac0aSEugeniy Paltsev #define CLK_SYS_USB 7 23e80dac0aSEugeniy Paltsev #define CLK_SYS_SDIO 8 24e80dac0aSEugeniy Paltsev #define CLK_SYS_HDMI 9 25e80dac0aSEugeniy Paltsev #define CLK_SYS_GFX_CORE 10 26e80dac0aSEugeniy Paltsev #define CLK_SYS_GFX_DMA 11 27e80dac0aSEugeniy Paltsev #define CLK_SYS_GFX_CFG 12 28e80dac0aSEugeniy Paltsev #define CLK_SYS_DMAC_CORE 13 29e80dac0aSEugeniy Paltsev #define CLK_SYS_DMAC_CFG 14 30e80dac0aSEugeniy Paltsev #define CLK_SYS_SDIO_REF 15 31e80dac0aSEugeniy Paltsev #define CLK_SYS_SPI_REF 16 32e80dac0aSEugeniy Paltsev #define CLK_SYS_I2C_REF 17 33e80dac0aSEugeniy Paltsev #define CLK_SYS_UART_REF 18 34e80dac0aSEugeniy Paltsev #define CLK_SYS_EBI_REF 19 35e80dac0aSEugeniy Paltsev #define CLK_TUN_PLL 20 36*075cbae1SEugeniy Paltsev #define CLK_TUN_TUN 21 37*075cbae1SEugeniy Paltsev #define CLK_TUN_ROM 22 38*075cbae1SEugeniy Paltsev #define CLK_TUN_PWM 23 39*075cbae1SEugeniy Paltsev #define CLK_HDMI_PLL 24 40*075cbae1SEugeniy Paltsev #define CLK_HDMI 25 41e80dac0aSEugeniy Paltsev 42e80dac0aSEugeniy Paltsev #endif /* __DT_BINDINGS_CLK_HSDK_CGU_H_ */ 43