1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */
2bae2f282SAndy Yan /*
3bae2f282SAndy Yan  * Copyright (c) 2017 Rockchip Electronics Co. Ltd.
4bae2f282SAndy Yan  * Author: Shawn Lin <shawn.lin@rock-chips.com>
5bae2f282SAndy Yan  */
6bae2f282SAndy Yan 
7bae2f282SAndy Yan #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H
8bae2f282SAndy Yan #define _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H
9bae2f282SAndy Yan 
10bae2f282SAndy Yan /* pll id */
11bae2f282SAndy Yan #define PLL_APLL			0
12bae2f282SAndy Yan #define PLL_DPLL			1
13bae2f282SAndy Yan #define PLL_GPLL			2
14bae2f282SAndy Yan #define ARMCLK				3
15bae2f282SAndy Yan 
16bae2f282SAndy Yan /* sclk gates (special clocks) */
17bae2f282SAndy Yan #define SCLK_MAC			64
18bae2f282SAndy Yan #define SCLK_SPI0			65
19bae2f282SAndy Yan #define SCLK_NANDC			67
20bae2f282SAndy Yan #define SCLK_SDMMC			68
21bae2f282SAndy Yan #define SCLK_SDIO			69
22bae2f282SAndy Yan #define SCLK_EMMC			71
23bae2f282SAndy Yan #define SCLK_UART0			72
24bae2f282SAndy Yan #define SCLK_UART1			73
25bae2f282SAndy Yan #define SCLK_UART2			74
26bae2f282SAndy Yan #define SCLK_I2S0			75
27bae2f282SAndy Yan #define SCLK_I2S1			76
28bae2f282SAndy Yan #define SCLK_I2S2			77
29bae2f282SAndy Yan #define SCLK_TIMER0			78
30bae2f282SAndy Yan #define SCLK_TIMER1			79
31bae2f282SAndy Yan #define SCLK_SFC			80
32bae2f282SAndy Yan #define SCLK_SDMMC_DRV			81
33bae2f282SAndy Yan #define SCLK_SDIO_DRV			82
34bae2f282SAndy Yan #define SCLK_EMMC_DRV			83
35bae2f282SAndy Yan #define SCLK_SDMMC_SAMPLE		84
36bae2f282SAndy Yan #define SCLK_SDIO_SAMPLE		85
37bae2f282SAndy Yan #define SCLK_EMMC_SAMPLE		86
38bae2f282SAndy Yan #define SCLK_MAC_RX			87
39bae2f282SAndy Yan #define SCLK_MAC_TX			88
40bae2f282SAndy Yan #define SCLK_MACREF			89
41bae2f282SAndy Yan #define SCLK_MACREF_OUT			90
422e4ce50dSDavid Wu #define SCLK_SARADC			91
43bae2f282SAndy Yan 
44bae2f282SAndy Yan 
45bae2f282SAndy Yan /* aclk gates */
46bae2f282SAndy Yan #define ACLK_DMAC			192
47bae2f282SAndy Yan #define ACLK_PRE			193
48bae2f282SAndy Yan #define ACLK_CORE			194
49bae2f282SAndy Yan #define ACLK_ENMCORE			195
50bae2f282SAndy Yan #define ACLK_GMAC			196
51bae2f282SAndy Yan 
52bae2f282SAndy Yan 
53bae2f282SAndy Yan /* pclk gates */
54bae2f282SAndy Yan #define PCLK_GPIO1			256
55bae2f282SAndy Yan #define PCLK_GPIO2			257
56bae2f282SAndy Yan #define PCLK_GPIO3			258
57bae2f282SAndy Yan #define PCLK_GRF			259
58bae2f282SAndy Yan #define PCLK_I2C1			260
59bae2f282SAndy Yan #define PCLK_I2C2			261
60bae2f282SAndy Yan #define PCLK_I2C3			262
61bae2f282SAndy Yan #define PCLK_SPI			263
62bae2f282SAndy Yan #define PCLK_SFC			264
63bae2f282SAndy Yan #define PCLK_UART0			265
64bae2f282SAndy Yan #define PCLK_UART1			266
65bae2f282SAndy Yan #define PCLK_UART2			267
66bae2f282SAndy Yan #define PCLK_TSADC			268
67bae2f282SAndy Yan #define PCLK_PWM			269
68bae2f282SAndy Yan #define PCLK_TIMER			270
69bae2f282SAndy Yan #define PCLK_PERI			271
70bae2f282SAndy Yan #define PCLK_GMAC			272
712e4ce50dSDavid Wu #define PCLK_SARADC			273
72bae2f282SAndy Yan 
73bae2f282SAndy Yan /* hclk gates */
74bae2f282SAndy Yan #define HCLK_I2S0_8CH			320
75bae2f282SAndy Yan #define HCLK_I2S1_8CH			321
76bae2f282SAndy Yan #define HCLK_I2S2_2CH			322
77bae2f282SAndy Yan #define HCLK_NANDC			323
78bae2f282SAndy Yan #define HCLK_SDMMC			324
79bae2f282SAndy Yan #define HCLK_SDIO			325
80bae2f282SAndy Yan #define HCLK_EMMC			326
81bae2f282SAndy Yan #define HCLK_PERI			327
82bae2f282SAndy Yan #define HCLK_SFC			328
83bae2f282SAndy Yan 
84bae2f282SAndy Yan #define CLK_NR_CLKS			(HCLK_SFC + 1)
85bae2f282SAndy Yan 
86bae2f282SAndy Yan /* reset id */
87bae2f282SAndy Yan #define SRST_CORE_PO_AD		0
88bae2f282SAndy Yan #define SRST_CORE_AD			1
89bae2f282SAndy Yan #define SRST_L2_AD			2
90bae2f282SAndy Yan #define SRST_CPU_NIU_AD		3
91bae2f282SAndy Yan #define SRST_CORE_PO			4
92bae2f282SAndy Yan #define SRST_CORE			5
93bae2f282SAndy Yan #define SRST_L2			6
94bae2f282SAndy Yan #define SRST_CORE_DBG			8
95bae2f282SAndy Yan #define PRST_DBG			9
96bae2f282SAndy Yan #define RST_DAP			10
97bae2f282SAndy Yan #define PRST_DBG_NIU			11
98bae2f282SAndy Yan #define ARST_STRC_SYS_AD		15
99bae2f282SAndy Yan 
100bae2f282SAndy Yan #define SRST_DDRPHY_CLKDIV		16
101bae2f282SAndy Yan #define SRST_DDRPHY			17
102bae2f282SAndy Yan #define PRST_DDRPHY			18
103bae2f282SAndy Yan #define PRST_HDMIPHY			19
104bae2f282SAndy Yan #define PRST_VDACPHY			20
105bae2f282SAndy Yan #define PRST_VADCPHY			21
106bae2f282SAndy Yan #define PRST_MIPI_CSI_PHY		22
107bae2f282SAndy Yan #define PRST_MIPI_DSI_PHY		23
108bae2f282SAndy Yan #define PRST_ACODEC			24
109bae2f282SAndy Yan #define ARST_BUS_NIU			25
110bae2f282SAndy Yan #define PRST_TOP_NIU			26
111bae2f282SAndy Yan #define ARST_INTMEM			27
112bae2f282SAndy Yan #define HRST_ROM			28
113bae2f282SAndy Yan #define ARST_DMAC			29
114bae2f282SAndy Yan #define SRST_MSCH_NIU			30
115bae2f282SAndy Yan #define PRST_MSCH_NIU			31
116bae2f282SAndy Yan 
117bae2f282SAndy Yan #define PRST_DDRUPCTL			32
118bae2f282SAndy Yan #define NRST_DDRUPCTL			33
119bae2f282SAndy Yan #define PRST_DDRMON			34
120bae2f282SAndy Yan #define HRST_I2S0_8CH			35
121bae2f282SAndy Yan #define MRST_I2S0_8CH			36
122bae2f282SAndy Yan #define HRST_I2S1_2CH			37
123bae2f282SAndy Yan #define MRST_IS21_2CH			38
124bae2f282SAndy Yan #define HRST_I2S2_2CH			39
125bae2f282SAndy Yan #define MRST_I2S2_2CH			40
126bae2f282SAndy Yan #define HRST_CRYPTO			41
127bae2f282SAndy Yan #define SRST_CRYPTO			42
128bae2f282SAndy Yan #define PRST_SPI			43
129bae2f282SAndy Yan #define SRST_SPI			44
130bae2f282SAndy Yan #define PRST_UART0			45
131bae2f282SAndy Yan #define PRST_UART1			46
132bae2f282SAndy Yan #define PRST_UART2			47
133bae2f282SAndy Yan 
134bae2f282SAndy Yan #define SRST_UART0			48
135bae2f282SAndy Yan #define SRST_UART1			49
136bae2f282SAndy Yan #define SRST_UART2			50
137bae2f282SAndy Yan #define PRST_I2C1			51
138bae2f282SAndy Yan #define PRST_I2C2			52
139bae2f282SAndy Yan #define PRST_I2C3			53
140bae2f282SAndy Yan #define SRST_I2C1			54
141bae2f282SAndy Yan #define SRST_I2C2			55
142bae2f282SAndy Yan #define SRST_I2C3			56
143bae2f282SAndy Yan #define PRST_PWM1			58
144bae2f282SAndy Yan #define SRST_PWM1			60
145bae2f282SAndy Yan #define PRST_WDT			61
146bae2f282SAndy Yan #define PRST_GPIO1			62
147bae2f282SAndy Yan #define PRST_GPIO2			63
148bae2f282SAndy Yan 
149bae2f282SAndy Yan #define PRST_GPIO3			64
150bae2f282SAndy Yan #define PRST_GRF			65
151bae2f282SAndy Yan #define PRST_EFUSE			66
152bae2f282SAndy Yan #define PRST_EFUSE512			67
153bae2f282SAndy Yan #define PRST_TIMER0			68
154bae2f282SAndy Yan #define SRST_TIMER0			69
155bae2f282SAndy Yan #define SRST_TIMER1			70
156bae2f282SAndy Yan #define PRST_TSADC			71
157bae2f282SAndy Yan #define SRST_TSADC			72
158bae2f282SAndy Yan #define PRST_SARADC			73
159bae2f282SAndy Yan #define SRST_SARADC			74
160bae2f282SAndy Yan #define HRST_SYSBUS			75
161bae2f282SAndy Yan #define PRST_USBGRF			76
162bae2f282SAndy Yan 
163bae2f282SAndy Yan #define ARST_PERIPH_NIU		80
164bae2f282SAndy Yan #define HRST_PERIPH_NIU		81
165bae2f282SAndy Yan #define PRST_PERIPH_NIU		82
166bae2f282SAndy Yan #define HRST_PERIPH			83
167bae2f282SAndy Yan #define HRST_SDMMC			84
168bae2f282SAndy Yan #define HRST_SDIO			85
169bae2f282SAndy Yan #define HRST_EMMC			86
170bae2f282SAndy Yan #define HRST_NANDC			87
171bae2f282SAndy Yan #define NRST_NANDC			88
172bae2f282SAndy Yan #define HRST_SFC			89
173bae2f282SAndy Yan #define SRST_SFC			90
174bae2f282SAndy Yan #define ARST_GMAC			91
175bae2f282SAndy Yan #define HRST_OTG			92
176bae2f282SAndy Yan #define SRST_OTG			93
177bae2f282SAndy Yan #define SRST_OTG_ADP			94
178bae2f282SAndy Yan #define HRST_HOST0			95
179bae2f282SAndy Yan 
180bae2f282SAndy Yan #define HRST_HOST0_AUX			96
181bae2f282SAndy Yan #define HRST_HOST0_ARB			97
182bae2f282SAndy Yan #define SRST_HOST0_EHCIPHY		98
183bae2f282SAndy Yan #define SRST_HOST0_UTMI		99
184bae2f282SAndy Yan #define SRST_USBPOR			100
185bae2f282SAndy Yan #define SRST_UTMI0			101
186bae2f282SAndy Yan #define SRST_UTMI1			102
187bae2f282SAndy Yan 
188bae2f282SAndy Yan #define ARST_VIO0_NIU			102
189bae2f282SAndy Yan #define ARST_VIO1_NIU			103
190bae2f282SAndy Yan #define HRST_VIO_NIU			104
191bae2f282SAndy Yan #define PRST_VIO_NIU			105
192bae2f282SAndy Yan #define ARST_VOP			106
193bae2f282SAndy Yan #define HRST_VOP			107
194bae2f282SAndy Yan #define DRST_VOP			108
195bae2f282SAndy Yan #define ARST_IEP			109
196bae2f282SAndy Yan #define HRST_IEP			110
197bae2f282SAndy Yan #define ARST_RGA			111
198bae2f282SAndy Yan #define HRST_RGA			112
199bae2f282SAndy Yan #define SRST_RGA			113
200bae2f282SAndy Yan #define PRST_CVBS			114
201bae2f282SAndy Yan #define PRST_HDMI			115
202bae2f282SAndy Yan #define SRST_HDMI			116
203bae2f282SAndy Yan #define PRST_MIPI_DSI			117
204bae2f282SAndy Yan 
205bae2f282SAndy Yan #define ARST_ISP_NIU			118
206bae2f282SAndy Yan #define HRST_ISP_NIU			119
207bae2f282SAndy Yan #define HRST_ISP			120
208bae2f282SAndy Yan #define SRST_ISP			121
209bae2f282SAndy Yan #define ARST_VIP0			122
210bae2f282SAndy Yan #define HRST_VIP0			123
211bae2f282SAndy Yan #define PRST_VIP0			124
212bae2f282SAndy Yan #define ARST_VIP1			125
213bae2f282SAndy Yan #define HRST_VIP1			126
214bae2f282SAndy Yan #define PRST_VIP1			127
215bae2f282SAndy Yan #define ARST_VIP2			128
216bae2f282SAndy Yan #define HRST_VIP2			129
217bae2f282SAndy Yan #define PRST_VIP2			120
218bae2f282SAndy Yan #define ARST_VIP3			121
219bae2f282SAndy Yan #define HRST_VIP3			122
220bae2f282SAndy Yan #define PRST_VIP4			123
221bae2f282SAndy Yan 
222bae2f282SAndy Yan #define PRST_CIF1TO4			124
223bae2f282SAndy Yan #define SRST_CVBS_CLK			125
224bae2f282SAndy Yan #define HRST_CVBS			126
225bae2f282SAndy Yan 
226bae2f282SAndy Yan #define ARST_VPU_NIU			140
227bae2f282SAndy Yan #define HRST_VPU_NIU			141
228bae2f282SAndy Yan #define ARST_VPU			142
229bae2f282SAndy Yan #define HRST_VPU			143
230bae2f282SAndy Yan #define ARST_RKVDEC_NIU		144
231bae2f282SAndy Yan #define HRST_RKVDEC_NIU		145
232bae2f282SAndy Yan #define ARST_RKVDEC			146
233bae2f282SAndy Yan #define HRST_RKVDEC			147
234bae2f282SAndy Yan #define SRST_RKVDEC_CABAC		148
235bae2f282SAndy Yan #define SRST_RKVDEC_CORE		149
236bae2f282SAndy Yan #define ARST_RKVENC_NIU		150
237bae2f282SAndy Yan #define HRST_RKVENC_NIU		151
238bae2f282SAndy Yan #define ARST_RKVENC			152
239bae2f282SAndy Yan #define HRST_RKVENC			153
240bae2f282SAndy Yan #define SRST_RKVENC_CORE		154
241bae2f282SAndy Yan 
242bae2f282SAndy Yan #define SRST_DSP_CORE			156
243bae2f282SAndy Yan #define SRST_DSP_SYS			157
244bae2f282SAndy Yan #define SRST_DSP_GLOBAL		158
245bae2f282SAndy Yan #define SRST_DSP_OECM			159
246bae2f282SAndy Yan #define PRST_DSP_IOP_NIU		160
247bae2f282SAndy Yan #define ARST_DSP_EPP_NIU		161
248bae2f282SAndy Yan #define ARST_DSP_EDP_NIU		162
249bae2f282SAndy Yan #define PRST_DSP_DBG_NIU		163
250bae2f282SAndy Yan #define PRST_DSP_CFG_NIU		164
251bae2f282SAndy Yan #define PRST_DSP_GRF			165
252bae2f282SAndy Yan #define PRST_DSP_MAILBOX		166
253bae2f282SAndy Yan #define PRST_DSP_INTC			167
254bae2f282SAndy Yan #define PRST_DSP_PFM_MON		169
255bae2f282SAndy Yan #define SRST_DSP_PFM_MON		170
256bae2f282SAndy Yan #define ARST_DSP_EDAP_NIU		171
257bae2f282SAndy Yan 
258bae2f282SAndy Yan #define SRST_PMU			172
259bae2f282SAndy Yan #define SRST_PMU_I2C0			173
260bae2f282SAndy Yan #define PRST_PMU_I2C0			174
261bae2f282SAndy Yan #define PRST_PMU_GPIO0			175
262bae2f282SAndy Yan #define PRST_PMU_INTMEM		176
263bae2f282SAndy Yan #define PRST_PMU_PWM0			177
264bae2f282SAndy Yan #define SRST_PMU_PWM0			178
265bae2f282SAndy Yan #define PRST_PMU_GRF			179
266bae2f282SAndy Yan #define SRST_PMU_NIU			180
267bae2f282SAndy Yan #define SRST_PMU_PVTM			181
268bae2f282SAndy Yan #define ARST_DSP_EDP_PERF		184
269bae2f282SAndy Yan #define ARST_DSP_EPP_PERF		185
270bae2f282SAndy Yan 
271bae2f282SAndy Yan #endif /* _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H */
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