1*9a26fc5aSMarek Vasut /* 2*9a26fc5aSMarek Vasut * Copyright (C) 2015 Renesas Electronics Corp. 3*9a26fc5aSMarek Vasut * 4*9a26fc5aSMarek Vasut * This program is free software; you can redistribute it and/or modify 5*9a26fc5aSMarek Vasut * it under the terms of the GNU General Public License as published by 6*9a26fc5aSMarek Vasut * the Free Software Foundation; either version 2 of the License, or 7*9a26fc5aSMarek Vasut * (at your option) any later version. 8*9a26fc5aSMarek Vasut */ 9*9a26fc5aSMarek Vasut 10*9a26fc5aSMarek Vasut #ifndef __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ 11*9a26fc5aSMarek Vasut #define __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ 12*9a26fc5aSMarek Vasut 13*9a26fc5aSMarek Vasut #include <dt-bindings/clock/renesas-cpg-mssr.h> 14*9a26fc5aSMarek Vasut 15*9a26fc5aSMarek Vasut /* r8a7794 CPG Core Clocks */ 16*9a26fc5aSMarek Vasut #define R8A7794_CLK_Z2 0 17*9a26fc5aSMarek Vasut #define R8A7794_CLK_ZG 1 18*9a26fc5aSMarek Vasut #define R8A7794_CLK_ZTR 2 19*9a26fc5aSMarek Vasut #define R8A7794_CLK_ZTRD2 3 20*9a26fc5aSMarek Vasut #define R8A7794_CLK_ZT 4 21*9a26fc5aSMarek Vasut #define R8A7794_CLK_ZX 5 22*9a26fc5aSMarek Vasut #define R8A7794_CLK_ZS 6 23*9a26fc5aSMarek Vasut #define R8A7794_CLK_HP 7 24*9a26fc5aSMarek Vasut #define R8A7794_CLK_I 8 25*9a26fc5aSMarek Vasut #define R8A7794_CLK_B 9 26*9a26fc5aSMarek Vasut #define R8A7794_CLK_LB 10 27*9a26fc5aSMarek Vasut #define R8A7794_CLK_P 11 28*9a26fc5aSMarek Vasut #define R8A7794_CLK_CL 12 29*9a26fc5aSMarek Vasut #define R8A7794_CLK_CP 13 30*9a26fc5aSMarek Vasut #define R8A7794_CLK_M2 14 31*9a26fc5aSMarek Vasut #define R8A7794_CLK_ADSP 15 32*9a26fc5aSMarek Vasut #define R8A7794_CLK_ZB3 16 33*9a26fc5aSMarek Vasut #define R8A7794_CLK_ZB3D2 17 34*9a26fc5aSMarek Vasut #define R8A7794_CLK_DDR 18 35*9a26fc5aSMarek Vasut #define R8A7794_CLK_SDH 19 36*9a26fc5aSMarek Vasut #define R8A7794_CLK_SD0 20 37*9a26fc5aSMarek Vasut #define R8A7794_CLK_SD2 21 38*9a26fc5aSMarek Vasut #define R8A7794_CLK_SD3 22 39*9a26fc5aSMarek Vasut #define R8A7794_CLK_MMC0 23 40*9a26fc5aSMarek Vasut #define R8A7794_CLK_MP 24 41*9a26fc5aSMarek Vasut #define R8A7794_CLK_QSPI 25 42*9a26fc5aSMarek Vasut #define R8A7794_CLK_CPEX 26 43*9a26fc5aSMarek Vasut #define R8A7794_CLK_RCAN 27 44*9a26fc5aSMarek Vasut #define R8A7794_CLK_R 28 45*9a26fc5aSMarek Vasut #define R8A7794_CLK_OSC 29 46*9a26fc5aSMarek Vasut 47*9a26fc5aSMarek Vasut #endif /* __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ */ 48