11eda014bSryan_chen /* SPDX-License-Identifier: GPL-2.0+ */ 21eda014bSryan_chen /* 3*d1e64dd1Sryan_chen * Copyright (C) ASPEED Technology Inc. 41eda014bSryan_chen */ 51eda014bSryan_chen 61eda014bSryan_chen /* Core Clocks */ 71eda014bSryan_chen #define PLL_DPLL 2 81eda014bSryan_chen #define PLL_D2PLL 3 91eda014bSryan_chen #define PLL_MPLL 4 101eda014bSryan_chen 111eda014bSryan_chen 121eda014bSryan_chen /* Bus Clocks, derived from core clocks */ 131eda014bSryan_chen #define BCLK_PCLK 101 141eda014bSryan_chen #define BCLK_LHCLK 102 151eda014bSryan_chen #define BCLK_MACCLK 103 161eda014bSryan_chen #define BCLK_SDCLK 104 171eda014bSryan_chen #define BCLK_ARMCLK 105 181eda014bSryan_chen 191eda014bSryan_chen #define MCLK_DDR 201 201eda014bSryan_chen 211eda014bSryan_chen /* Special clocks */ 221eda014bSryan_chen #define PCLK_UART1 501 231eda014bSryan_chen #define PCLK_UART2 502 241eda014bSryan_chen #define PCLK_UART3 503 251eda014bSryan_chen #define PCLK_UART4 504 261eda014bSryan_chen #define PCLK_UART5 505 271eda014bSryan_chen #define PCLK_MAC1 506 281eda014bSryan_chen #define PCLK_MAC2 507 291eda014bSryan_chen 30*d1e64dd1Sryan_chen /* come from linux kernel */ 311eda014bSryan_chen 32*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_ECLK 0 33*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_GCLK 1 34*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_MCLK 2 35*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_VCLK 3 36*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_BCLK 4 37*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_DCLK 5 38*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_REFCLK 6 39*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_USBPORT2CLK 7 40*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_LCLK 8 41*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_USBUHCICLK 9 42*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_D1CLK 10 43*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_YCLK 11 44*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_USBPORT1CLK 12 45*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_UART1CLK 13 46*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_UART2CLK 14 47*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_UART5CLK 15 48*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_ESPICLK 16 49*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_MAC1CLK 17 50*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_MAC2CLK 18 51*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_RSACLK 19 52*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_UART3CLK 20 53*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_UART4CLK 21 54*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_SDCLK 22 55*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_LHCCLK 23 56*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_SDEXTCLK 24 57*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_EMMCCLK 25 58*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_EMMCEXTCLK 26 591eda014bSryan_chen 60*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_UART6CLK 27 61*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_UART7CLK 28 62*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_UART8CLK 29 63*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_UART9CLK 30 64*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_UART10CLK 31 65*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_UART11CLK 32 66*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_UART12CLK 33 67*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_UART13CLK 34 681eda014bSryan_chen 69*d1e64dd1Sryan_chen #define ASPEED_CLK_HPLL 35 70*d1e64dd1Sryan_chen #define ASPEED_CLK_AHB 36 71*d1e64dd1Sryan_chen #define ASPEED_CLK_APB 37 72*d1e64dd1Sryan_chen #define ASPEED_CLK_UART 38 73*d1e64dd1Sryan_chen #define ASPEED_CLK_SDIO 39 74*d1e64dd1Sryan_chen #define ASPEED_CLK_ECLK 40 75*d1e64dd1Sryan_chen #define ASPEED_CLK_ECLK_MUX 41 76*d1e64dd1Sryan_chen #define ASPEED_CLK_LHCLK 42 77*d1e64dd1Sryan_chen #define ASPEED_CLK_MAC 43 78*d1e64dd1Sryan_chen #define ASPEED_CLK_BCLK 44 79*d1e64dd1Sryan_chen #define ASPEED_CLK_MPLL 45 80*d1e64dd1Sryan_chen #define ASPEED_CLK_24M 46 81*d1e64dd1Sryan_chen #define ASPEED_CLK_EMMC 47 82*d1e64dd1Sryan_chen #define ASPEED_CLK_UARTX 48 831eda014bSryan_chen 84