1*1eda014bSryan_chen /* SPDX-License-Identifier: GPL-2.0+ */ 2*1eda014bSryan_chen /* 3*1eda014bSryan_chen */ 4*1eda014bSryan_chen 5*1eda014bSryan_chen /* Core Clocks */ 6*1eda014bSryan_chen #define PLL_HPLL 1 7*1eda014bSryan_chen #define PLL_DPLL 2 8*1eda014bSryan_chen #define PLL_D2PLL 3 9*1eda014bSryan_chen #define PLL_MPLL 4 10*1eda014bSryan_chen #define ARMCLK 5 11*1eda014bSryan_chen 12*1eda014bSryan_chen 13*1eda014bSryan_chen /* Bus Clocks, derived from core clocks */ 14*1eda014bSryan_chen #define BCLK_PCLK 101 15*1eda014bSryan_chen #define BCLK_LHCLK 102 16*1eda014bSryan_chen #define BCLK_MACCLK 103 17*1eda014bSryan_chen #define BCLK_SDCLK 104 18*1eda014bSryan_chen #define BCLK_ARMCLK 105 19*1eda014bSryan_chen #define BCLK_HCLK 106 20*1eda014bSryan_chen 21*1eda014bSryan_chen #define MCLK_DDR 201 22*1eda014bSryan_chen 23*1eda014bSryan_chen /* Special clocks */ 24*1eda014bSryan_chen #define PCLK_UART1 501 25*1eda014bSryan_chen #define PCLK_UART2 502 26*1eda014bSryan_chen #define PCLK_UART3 503 27*1eda014bSryan_chen #define PCLK_UART4 504 28*1eda014bSryan_chen #define PCLK_UART5 505 29*1eda014bSryan_chen #define PCLK_MAC1 506 30*1eda014bSryan_chen #define PCLK_MAC2 507 31*1eda014bSryan_chen 32*1eda014bSryan_chen 33*1eda014bSryan_chen 34*1eda014bSryan_chen #define ASPEED_CLK_UART1 46 35*1eda014bSryan_chen #define ASPEED_CLK_UART2 47 36*1eda014bSryan_chen #define ASPEED_CLK_UART3 48 37*1eda014bSryan_chen #define ASPEED_CLK_UART4 49 38*1eda014bSryan_chen #define ASPEED_CLK_UART5 50 39*1eda014bSryan_chen 40*1eda014bSryan_chen 41*1eda014bSryan_chen 42*1eda014bSryan_chen 43