1*9604e92eSryan_chen /* SPDX-License-Identifier: GPL-2.0+ */ 2*9604e92eSryan_chen /* 3*9604e92eSryan_chen * Copyright 2016 Google Inc. 4*9604e92eSryan_chen */ 5*9604e92eSryan_chen 6*9604e92eSryan_chen /* Core Clocks */ 7*9604e92eSryan_chen #define PLL_HPLL 1 8*9604e92eSryan_chen #define PLL_DPLL 2 9*9604e92eSryan_chen #define PLL_D2PLL 3 10*9604e92eSryan_chen #define PLL_MPLL 4 11*9604e92eSryan_chen #define ARMCLK 5 12*9604e92eSryan_chen 13*9604e92eSryan_chen 14*9604e92eSryan_chen /* Bus Clocks, derived from core clocks */ 15*9604e92eSryan_chen #define BCLK_PCLK 101 16*9604e92eSryan_chen #define BCLK_LHCLK 102 17*9604e92eSryan_chen #define BCLK_MACCLK 103 18*9604e92eSryan_chen #define BCLK_SDCLK 104 19*9604e92eSryan_chen #define BCLK_ARMCLK 105 20*9604e92eSryan_chen #define BCLK_HCLK 106 21*9604e92eSryan_chen 22*9604e92eSryan_chen #define MCLK_DDR 201 23*9604e92eSryan_chen 24*9604e92eSryan_chen /* Special clocks */ 25*9604e92eSryan_chen #define PCLK_UART1 501 26*9604e92eSryan_chen #define PCLK_UART2 502 27*9604e92eSryan_chen #define PCLK_UART3 503 28*9604e92eSryan_chen #define PCLK_UART4 504 29*9604e92eSryan_chen #define PCLK_UART5 505 30*9604e92eSryan_chen #define PCLK_MAC1 506 31*9604e92eSryan_chen #define PCLK_MAC2 507 32