1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/mrc/quark.h> 9#include <dt-bindings/interrupt-router/intel-irq.h> 10 11/include/ "skeleton.dtsi" 12/include/ "reset.dtsi" 13/include/ "rtc.dtsi" 14/include/ "tsc_timer.dtsi" 15 16/ { 17 model = "Intel Galileo"; 18 compatible = "intel,galileo", "intel,quark"; 19 20 aliases { 21 spi0 = &spi; 22 }; 23 24 config { 25 silent_console = <0>; 26 }; 27 28 chosen { 29 stdout-path = &pciuart0; 30 }; 31 32 cpus { 33 #address-cells = <1>; 34 #size-cells = <0>; 35 36 cpu@0 { 37 device_type = "cpu"; 38 compatible = "cpu-x86"; 39 reg = <0>; 40 intel,apic-id = <0>; 41 }; 42 }; 43 44 tsc-timer { 45 clock-frequency = <400000000>; 46 }; 47 48 mrc { 49 compatible = "intel,quark-mrc"; 50 flags = <MRC_FLAG_SCRAMBLE_EN>; 51 dram-width = <DRAM_WIDTH_X8>; 52 dram-speed = <DRAM_FREQ_800>; 53 dram-type = <DRAM_TYPE_DDR3>; 54 rank-mask = <DRAM_RANK(0)>; 55 chan-mask = <DRAM_CHANNEL(0)>; 56 chan-width = <DRAM_CHANNEL_WIDTH_X16>; 57 addr-mode = <DRAM_ADDR_MODE0>; 58 refresh-rate = <DRAM_REFRESH_RATE_785US>; 59 sr-temp-range = <DRAM_SRT_RANGE_NORMAL>; 60 ron-value = <DRAM_RON_34OHM>; 61 rtt-nom-value = <DRAM_RTT_NOM_120OHM>; 62 rd-odt-value = <DRAM_RD_ODT_OFF>; 63 dram-density = <DRAM_DENSITY_1G>; 64 dram-cl = <6>; 65 dram-ras = <0x0000927c>; 66 dram-wtr = <0x00002710>; 67 dram-rrd = <0x00002710>; 68 dram-faw = <0x00009c40>; 69 }; 70 71 pci { 72 #address-cells = <3>; 73 #size-cells = <2>; 74 compatible = "pci-x86"; 75 u-boot,dm-pre-reloc; 76 ranges = <0x02000000 0x0 0x90000000 0x90000000 0 0x20000000 77 0x42000000 0x0 0xb0000000 0xb0000000 0 0x20000000 78 0x01000000 0x0 0x2000 0x2000 0 0xe000>; 79 80 pciuart0: uart@14,5 { 81 compatible = "pci8086,0936.00", 82 "pci8086,0936", 83 "pciclass,070002", 84 "pciclass,0700", 85 "ns16550"; 86 u-boot,dm-pre-reloc; 87 reg = <0x0000a500 0x0 0x0 0x0 0x0 88 0x0200a510 0x0 0x0 0x0 0x0>; 89 reg-shift = <2>; 90 clock-frequency = <44236800>; 91 current-speed = <115200>; 92 }; 93 94 pch@1f,0 { 95 reg = <0x0000f800 0 0 0 0>; 96 compatible = "intel,pch7"; 97 #address-cells = <1>; 98 #size-cells = <1>; 99 100 irq-router { 101 compatible = "intel,irq-router"; 102 intel,pirq-config = "pci"; 103 intel,actl-addr = <0x58>; 104 intel,pirq-link = <0x60 8>; 105 intel,pirq-mask = <0xdef8>; 106 intel,pirq-routing = < 107 PCI_BDF(0, 20, 0) INTA PIRQE 108 PCI_BDF(0, 20, 1) INTB PIRQF 109 PCI_BDF(0, 20, 2) INTC PIRQG 110 PCI_BDF(0, 20, 3) INTD PIRQH 111 PCI_BDF(0, 20, 4) INTA PIRQE 112 PCI_BDF(0, 20, 5) INTB PIRQF 113 PCI_BDF(0, 20, 6) INTC PIRQG 114 PCI_BDF(0, 20, 7) INTD PIRQH 115 PCI_BDF(0, 21, 0) INTA PIRQE 116 PCI_BDF(0, 21, 1) INTB PIRQF 117 PCI_BDF(0, 21, 2) INTC PIRQG 118 PCI_BDF(0, 23, 0) INTA PIRQA 119 PCI_BDF(0, 23, 1) INTB PIRQB 120 121 /* PCIe root ports downstream interrupts */ 122 PCI_BDF(1, 0, 0) INTA PIRQA 123 PCI_BDF(1, 0, 0) INTB PIRQB 124 PCI_BDF(1, 0, 0) INTC PIRQC 125 PCI_BDF(1, 0, 0) INTD PIRQD 126 PCI_BDF(2, 0, 0) INTA PIRQB 127 PCI_BDF(2, 0, 0) INTB PIRQC 128 PCI_BDF(2, 0, 0) INTC PIRQD 129 PCI_BDF(2, 0, 0) INTD PIRQA 130 >; 131 }; 132 133 spi: spi { 134 #address-cells = <1>; 135 #size-cells = <0>; 136 compatible = "intel,ich7-spi"; 137 spi-flash@0 { 138 #size-cells = <1>; 139 #address-cells = <1>; 140 reg = <0>; 141 compatible = "winbond,w25q64", 142 "spi-flash"; 143 memory-map = <0xff800000 0x00800000>; 144 rw-mrc-cache { 145 label = "rw-mrc-cache"; 146 reg = <0x00010000 0x00010000>; 147 }; 148 }; 149 }; 150 151 gpioa { 152 compatible = "intel,ich6-gpio"; 153 u-boot,dm-pre-reloc; 154 reg = <0 0x20>; 155 bank-name = "A"; 156 }; 157 158 gpiob { 159 compatible = "intel,ich6-gpio"; 160 u-boot,dm-pre-reloc; 161 reg = <0x20 0x20>; 162 bank-name = "B"; 163 }; 164 }; 165 }; 166 167}; 168