1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/interrupt-router/intel-irq.h> 9 10/include/ "skeleton.dtsi" 11/include/ "serial.dtsi" 12/include/ "keyboard.dtsi" 13/include/ "pcspkr.dtsi" 14/include/ "reset.dtsi" 15/include/ "rtc.dtsi" 16/include/ "tsc_timer.dtsi" 17 18/ { 19 model = "Intel Crown Bay"; 20 compatible = "intel,crownbay", "intel,queensbay"; 21 22 aliases { 23 spi0 = &spi; 24 }; 25 26 config { 27 silent_console = <0>; 28 }; 29 30 cpus { 31 #address-cells = <1>; 32 #size-cells = <0>; 33 34 cpu@0 { 35 device_type = "cpu"; 36 compatible = "cpu-x86"; 37 reg = <0>; 38 intel,apic-id = <0>; 39 }; 40 41 cpu@1 { 42 device_type = "cpu"; 43 compatible = "cpu-x86"; 44 reg = <1>; 45 intel,apic-id = <1>; 46 }; 47 48 }; 49 50 chosen { 51 /* 52 * By default the legacy superio serial port is used as the 53 * U-Boot serial console. If we want to use UART from Topcliff 54 * PCH as the console, change this property to &pciuart#. 55 * 56 * For example, stdout-path = &pciuart0 will use the first 57 * UART on Topcliff PCH. 58 */ 59 stdout-path = "/serial"; 60 }; 61 62 microcode { 63 update@0 { 64#include "microcode/m0220661105_cv.dtsi" 65 }; 66 }; 67 68 pci { 69 #address-cells = <3>; 70 #size-cells = <2>; 71 compatible = "pci-x86"; 72 u-boot,dm-pre-reloc; 73 ranges = <0x02000000 0x0 0x40000000 0x40000000 0 0x80000000 74 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 75 0x01000000 0x0 0x2000 0x2000 0 0xe000>; 76 77 pcie@17,0 { 78 #address-cells = <3>; 79 #size-cells = <2>; 80 compatible = "pci-bridge"; 81 u-boot,dm-pre-reloc; 82 reg = <0x0000b800 0x0 0x0 0x0 0x0>; 83 84 topcliff@0,0 { 85 #address-cells = <3>; 86 #size-cells = <2>; 87 compatible = "pci-bridge"; 88 u-boot,dm-pre-reloc; 89 reg = <0x00010000 0x0 0x0 0x0 0x0>; 90 91 pciuart0: uart@a,1 { 92 compatible = "pci8086,8811.00", 93 "pci8086,8811", 94 "pciclass,070002", 95 "pciclass,0700", 96 "ns16550"; 97 u-boot,dm-pre-reloc; 98 reg = <0x00025100 0x0 0x0 0x0 0x0 99 0x01025110 0x0 0x0 0x0 0x0>; 100 reg-shift = <0>; 101 clock-frequency = <1843200>; 102 current-speed = <115200>; 103 }; 104 105 pciuart1: uart@a,2 { 106 compatible = "pci8086,8812.00", 107 "pci8086,8812", 108 "pciclass,070002", 109 "pciclass,0700", 110 "ns16550"; 111 u-boot,dm-pre-reloc; 112 reg = <0x00025200 0x0 0x0 0x0 0x0 113 0x01025210 0x0 0x0 0x0 0x0>; 114 reg-shift = <0>; 115 clock-frequency = <1843200>; 116 current-speed = <115200>; 117 }; 118 119 pciuart2: uart@a,3 { 120 compatible = "pci8086,8813.00", 121 "pci8086,8813", 122 "pciclass,070002", 123 "pciclass,0700", 124 "ns16550"; 125 u-boot,dm-pre-reloc; 126 reg = <0x00025300 0x0 0x0 0x0 0x0 127 0x01025310 0x0 0x0 0x0 0x0>; 128 reg-shift = <0>; 129 clock-frequency = <1843200>; 130 current-speed = <115200>; 131 }; 132 133 pciuart3: uart@a,4 { 134 compatible = "pci8086,8814.00", 135 "pci8086,8814", 136 "pciclass,070002", 137 "pciclass,0700", 138 "ns16550"; 139 u-boot,dm-pre-reloc; 140 reg = <0x00025400 0x0 0x0 0x0 0x0 141 0x01025410 0x0 0x0 0x0 0x0>; 142 reg-shift = <0>; 143 clock-frequency = <1843200>; 144 current-speed = <115200>; 145 }; 146 }; 147 }; 148 149 pch@1f,0 { 150 reg = <0x0000f800 0 0 0 0>; 151 compatible = "intel,pch7"; 152 #address-cells = <1>; 153 #size-cells = <1>; 154 155 irq-router { 156 compatible = "intel,irq-router"; 157 intel,pirq-config = "pci"; 158 intel,actl-addr = <0x58>; 159 intel,pirq-link = <0x60 8>; 160 intel,pirq-mask = <0xcee0>; 161 intel,pirq-routing = < 162 /* TunnelCreek PCI devices */ 163 PCI_BDF(0, 2, 0) INTA PIRQE 164 PCI_BDF(0, 3, 0) INTA PIRQF 165 PCI_BDF(0, 23, 0) INTA PIRQA 166 PCI_BDF(0, 23, 0) INTB PIRQB 167 PCI_BDF(0, 23, 0) INTC PIRQC 168 PCI_BDF(0, 23, 0) INTD PIRQD 169 PCI_BDF(0, 24, 0) INTA PIRQB 170 PCI_BDF(0, 24, 0) INTB PIRQC 171 PCI_BDF(0, 24, 0) INTC PIRQD 172 PCI_BDF(0, 24, 0) INTD PIRQA 173 PCI_BDF(0, 25, 0) INTA PIRQC 174 PCI_BDF(0, 25, 0) INTB PIRQD 175 PCI_BDF(0, 25, 0) INTC PIRQA 176 PCI_BDF(0, 25, 0) INTD PIRQB 177 PCI_BDF(0, 26, 0) INTA PIRQD 178 PCI_BDF(0, 26, 0) INTB PIRQA 179 PCI_BDF(0, 26, 0) INTC PIRQB 180 PCI_BDF(0, 26, 0) INTD PIRQC 181 PCI_BDF(0, 27, 0) INTA PIRQG 182 /* 183 * Topcliff PCI devices 184 * 185 * Note on the Crown Bay board, Topcliff 186 * chipset is connected to TunnelCreek 187 * PCIe port 0, so its bus number is 1 188 * for its PCIe port and 2 for its PCI 189 * devices per U-Boot current PCI bus 190 * enumeration algorithm. 191 */ 192 PCI_BDF(1, 0, 0) INTA PIRQA 193 PCI_BDF(2, 0, 1) INTA PIRQA 194 PCI_BDF(2, 0, 2) INTA PIRQA 195 PCI_BDF(2, 2, 0) INTB PIRQD 196 PCI_BDF(2, 2, 1) INTB PIRQD 197 PCI_BDF(2, 2, 2) INTB PIRQD 198 PCI_BDF(2, 2, 3) INTB PIRQD 199 PCI_BDF(2, 2, 4) INTB PIRQD 200 PCI_BDF(2, 4, 0) INTC PIRQC 201 PCI_BDF(2, 4, 1) INTC PIRQC 202 PCI_BDF(2, 6, 0) INTD PIRQB 203 PCI_BDF(2, 8, 0) INTA PIRQA 204 PCI_BDF(2, 8, 1) INTA PIRQA 205 PCI_BDF(2, 8, 2) INTA PIRQA 206 PCI_BDF(2, 8, 3) INTA PIRQA 207 PCI_BDF(2, 10, 0) INTB PIRQD 208 PCI_BDF(2, 10, 1) INTB PIRQD 209 PCI_BDF(2, 10, 2) INTB PIRQD 210 PCI_BDF(2, 10, 3) INTB PIRQD 211 PCI_BDF(2, 10, 4) INTB PIRQD 212 PCI_BDF(2, 12, 0) INTC PIRQC 213 PCI_BDF(2, 12, 1) INTC PIRQC 214 PCI_BDF(2, 12, 2) INTC PIRQC 215 PCI_BDF(2, 12, 3) INTC PIRQC 216 PCI_BDF(2, 12, 4) INTC PIRQC 217 >; 218 }; 219 220 spi: spi { 221 #address-cells = <1>; 222 #size-cells = <0>; 223 compatible = "intel,ich7-spi"; 224 spi-flash@0 { 225 reg = <0>; 226 compatible = "sst,25vf016b", 227 "spi-flash"; 228 memory-map = <0xffe00000 0x00200000>; 229 }; 230 }; 231 232 gpioa { 233 compatible = "intel,ich6-gpio"; 234 u-boot,dm-pre-reloc; 235 reg = <0 0x20>; 236 bank-name = "A"; 237 }; 238 239 gpiob { 240 compatible = "intel,ich6-gpio"; 241 u-boot,dm-pre-reloc; 242 reg = <0x20 0x20>; 243 bank-name = "B"; 244 }; 245 }; 246 }; 247 248}; 249