1/* 2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/interrupt-router/intel-irq.h> 10 11/include/ "skeleton.dtsi" 12/include/ "serial.dtsi" 13/include/ "rtc.dtsi" 14 15/ { 16 model = "Intel Crown Bay"; 17 compatible = "intel,crownbay", "intel,queensbay"; 18 19 aliases { 20 spi0 = "/spi"; 21 }; 22 23 config { 24 silent_console = <0>; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 cpu@0 { 32 device_type = "cpu"; 33 compatible = "cpu-x86"; 34 reg = <0>; 35 intel,apic-id = <0>; 36 }; 37 38 cpu@1 { 39 device_type = "cpu"; 40 compatible = "cpu-x86"; 41 reg = <1>; 42 intel,apic-id = <1>; 43 }; 44 45 }; 46 47 gpioa { 48 compatible = "intel,ich6-gpio"; 49 u-boot,dm-pre-reloc; 50 reg = <0 0x20>; 51 bank-name = "A"; 52 }; 53 54 gpiob { 55 compatible = "intel,ich6-gpio"; 56 u-boot,dm-pre-reloc; 57 reg = <0x20 0x20>; 58 bank-name = "B"; 59 }; 60 61 chosen { 62 /* 63 * By default the legacy superio serial port is used as the 64 * U-Boot serial console. If we want to use UART from Topcliff 65 * PCH as the console, change this property to &pciuart#. 66 * 67 * For example, stdout-path = &pciuart0 will use the first 68 * UART on Topcliff PCH. 69 */ 70 stdout-path = "/serial"; 71 }; 72 73 spi { 74 #address-cells = <1>; 75 #size-cells = <0>; 76 compatible = "intel,ich-spi"; 77 spi-flash@0 { 78 reg = <0>; 79 compatible = "sst,25vf016b", "spi-flash"; 80 memory-map = <0xffe00000 0x00200000>; 81 }; 82 }; 83 84 microcode { 85 update@0 { 86#include "microcode/m0220661105_cv.dtsi" 87 }; 88 }; 89 90 pci { 91 #address-cells = <3>; 92 #size-cells = <2>; 93 compatible = "pci-x86"; 94 device_type = "pci"; 95 u-boot,dm-pre-reloc; 96 ranges = <0x02000000 0x0 0x40000000 0x40000000 0 0x80000000 97 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 98 0x01000000 0x0 0x2000 0x2000 0 0xe000>; 99 100 pcie@17,0 { 101 #address-cells = <3>; 102 #size-cells = <2>; 103 compatible = "intel,pci"; 104 device_type = "pci"; 105 106 topcliff@0,0 { 107 #address-cells = <3>; 108 #size-cells = <2>; 109 compatible = "intel,pci"; 110 device_type = "pci"; 111 112 pciuart0: uart@a,1 { 113 compatible = "pci8086,8811.00", 114 "pci8086,8811", 115 "pciclass,070002", 116 "pciclass,0700", 117 "x86-uart"; 118 reg = <0x00025100 0x0 0x0 0x0 0x0 119 0x01025110 0x0 0x0 0x0 0x0>; 120 reg-shift = <0>; 121 clock-frequency = <1843200>; 122 current-speed = <115200>; 123 }; 124 125 pciuart1: uart@a,2 { 126 compatible = "pci8086,8812.00", 127 "pci8086,8812", 128 "pciclass,070002", 129 "pciclass,0700", 130 "x86-uart"; 131 reg = <0x00025200 0x0 0x0 0x0 0x0 132 0x01025210 0x0 0x0 0x0 0x0>; 133 reg-shift = <0>; 134 clock-frequency = <1843200>; 135 current-speed = <115200>; 136 }; 137 138 pciuart2: uart@a,3 { 139 compatible = "pci8086,8813.00", 140 "pci8086,8813", 141 "pciclass,070002", 142 "pciclass,0700", 143 "x86-uart"; 144 reg = <0x00025300 0x0 0x0 0x0 0x0 145 0x01025310 0x0 0x0 0x0 0x0>; 146 reg-shift = <0>; 147 clock-frequency = <1843200>; 148 current-speed = <115200>; 149 }; 150 151 pciuart3: uart@a,4 { 152 compatible = "pci8086,8814.00", 153 "pci8086,8814", 154 "pciclass,070002", 155 "pciclass,0700", 156 "x86-uart"; 157 reg = <0x00025400 0x0 0x0 0x0 0x0 158 0x01025410 0x0 0x0 0x0 0x0>; 159 reg-shift = <0>; 160 clock-frequency = <1843200>; 161 current-speed = <115200>; 162 }; 163 }; 164 }; 165 166 irq-router@1f,0 { 167 reg = <0x0000f800 0 0 0 0>; 168 compatible = "intel,irq-router"; 169 intel,pirq-config = "pci"; 170 intel,pirq-link = <0x60 8>; 171 intel,pirq-mask = <0xdee0>; 172 intel,pirq-routing = < 173 /* TunnelCreek PCI devices */ 174 PCI_BDF(0, 2, 0) INTA PIRQE 175 PCI_BDF(0, 3, 0) INTA PIRQF 176 PCI_BDF(0, 23, 0) INTA PIRQA 177 PCI_BDF(0, 23, 0) INTB PIRQB 178 PCI_BDF(0, 23, 0) INTC PIRQC 179 PCI_BDF(0, 23, 0) INTD PIRQD 180 PCI_BDF(0, 24, 0) INTA PIRQB 181 PCI_BDF(0, 24, 0) INTB PIRQC 182 PCI_BDF(0, 24, 0) INTC PIRQD 183 PCI_BDF(0, 24, 0) INTD PIRQA 184 PCI_BDF(0, 25, 0) INTA PIRQC 185 PCI_BDF(0, 25, 0) INTB PIRQD 186 PCI_BDF(0, 25, 0) INTC PIRQA 187 PCI_BDF(0, 25, 0) INTD PIRQB 188 PCI_BDF(0, 26, 0) INTA PIRQD 189 PCI_BDF(0, 26, 0) INTB PIRQA 190 PCI_BDF(0, 26, 0) INTC PIRQB 191 PCI_BDF(0, 26, 0) INTD PIRQC 192 PCI_BDF(0, 27, 0) INTA PIRQG 193 /* 194 * Topcliff PCI devices 195 * 196 * Note on the Crown Bay board, Topcliff chipset 197 * is connected to TunnelCreek PCIe port 0, so 198 * its bus number is 1 for its PCIe port and 2 199 * for its PCI devices per U-Boot current PCI 200 * bus enumeration algorithm. 201 */ 202 PCI_BDF(1, 0, 0) INTA PIRQA 203 PCI_BDF(2, 0, 1) INTA PIRQA 204 PCI_BDF(2, 0, 2) INTA PIRQA 205 PCI_BDF(2, 2, 0) INTB PIRQD 206 PCI_BDF(2, 2, 1) INTB PIRQD 207 PCI_BDF(2, 2, 2) INTB PIRQD 208 PCI_BDF(2, 2, 3) INTB PIRQD 209 PCI_BDF(2, 2, 4) INTB PIRQD 210 PCI_BDF(2, 4, 0) INTC PIRQC 211 PCI_BDF(2, 4, 1) INTC PIRQC 212 PCI_BDF(2, 6, 0) INTD PIRQB 213 PCI_BDF(2, 8, 0) INTA PIRQA 214 PCI_BDF(2, 8, 1) INTA PIRQA 215 PCI_BDF(2, 8, 2) INTA PIRQA 216 PCI_BDF(2, 8, 3) INTA PIRQA 217 PCI_BDF(2, 10, 0) INTB PIRQD 218 PCI_BDF(2, 10, 1) INTB PIRQD 219 PCI_BDF(2, 10, 2) INTB PIRQD 220 PCI_BDF(2, 10, 3) INTB PIRQD 221 PCI_BDF(2, 10, 4) INTB PIRQD 222 PCI_BDF(2, 12, 0) INTC PIRQC 223 PCI_BDF(2, 12, 1) INTC PIRQC 224 PCI_BDF(2, 12, 2) INTC PIRQC 225 PCI_BDF(2, 12, 3) INTC PIRQC 226 PCI_BDF(2, 12, 4) INTC PIRQC 227 >; 228 }; 229 }; 230 231}; 232