1/* 2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/interrupt-router/intel-irq.h> 10 11/include/ "skeleton.dtsi" 12/include/ "serial.dtsi" 13/include/ "keyboard.dtsi" 14/include/ "rtc.dtsi" 15 16/ { 17 model = "Intel Crown Bay"; 18 compatible = "intel,crownbay", "intel,queensbay"; 19 20 aliases { 21 spi0 = "/spi"; 22 }; 23 24 config { 25 silent_console = <0>; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 cpu@0 { 33 device_type = "cpu"; 34 compatible = "cpu-x86"; 35 reg = <0>; 36 intel,apic-id = <0>; 37 }; 38 39 cpu@1 { 40 device_type = "cpu"; 41 compatible = "cpu-x86"; 42 reg = <1>; 43 intel,apic-id = <1>; 44 }; 45 46 }; 47 48 gpioa { 49 compatible = "intel,ich6-gpio"; 50 u-boot,dm-pre-reloc; 51 reg = <0 0x20>; 52 bank-name = "A"; 53 }; 54 55 gpiob { 56 compatible = "intel,ich6-gpio"; 57 u-boot,dm-pre-reloc; 58 reg = <0x20 0x20>; 59 bank-name = "B"; 60 }; 61 62 chosen { 63 /* 64 * By default the legacy superio serial port is used as the 65 * U-Boot serial console. If we want to use UART from Topcliff 66 * PCH as the console, change this property to &pciuart#. 67 * 68 * For example, stdout-path = &pciuart0 will use the first 69 * UART on Topcliff PCH. 70 */ 71 stdout-path = "/serial"; 72 }; 73 74 spi { 75 #address-cells = <1>; 76 #size-cells = <0>; 77 compatible = "intel,ich-spi"; 78 spi-flash@0 { 79 reg = <0>; 80 compatible = "sst,25vf016b", "spi-flash"; 81 memory-map = <0xffe00000 0x00200000>; 82 }; 83 }; 84 85 microcode { 86 update@0 { 87#include "microcode/m0220661105_cv.dtsi" 88 }; 89 }; 90 91 pci { 92 #address-cells = <3>; 93 #size-cells = <2>; 94 compatible = "pci-x86"; 95 u-boot,dm-pre-reloc; 96 ranges = <0x02000000 0x0 0x40000000 0x40000000 0 0x80000000 97 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 98 0x01000000 0x0 0x2000 0x2000 0 0xe000>; 99 100 pcie@17,0 { 101 #address-cells = <3>; 102 #size-cells = <2>; 103 compatible = "pci-bridge"; 104 u-boot,dm-pre-reloc; 105 reg = <0x0000b800 0x0 0x0 0x0 0x0>; 106 107 topcliff@0,0 { 108 #address-cells = <3>; 109 #size-cells = <2>; 110 compatible = "pci-bridge"; 111 u-boot,dm-pre-reloc; 112 reg = <0x00010000 0x0 0x0 0x0 0x0>; 113 114 pciuart0: uart@a,1 { 115 compatible = "pci8086,8811.00", 116 "pci8086,8811", 117 "pciclass,070002", 118 "pciclass,0700", 119 "x86-uart"; 120 u-boot,dm-pre-reloc; 121 reg = <0x00025100 0x0 0x0 0x0 0x0 122 0x01025110 0x0 0x0 0x0 0x0>; 123 reg-shift = <0>; 124 clock-frequency = <1843200>; 125 current-speed = <115200>; 126 }; 127 128 pciuart1: uart@a,2 { 129 compatible = "pci8086,8812.00", 130 "pci8086,8812", 131 "pciclass,070002", 132 "pciclass,0700", 133 "x86-uart"; 134 u-boot,dm-pre-reloc; 135 reg = <0x00025200 0x0 0x0 0x0 0x0 136 0x01025210 0x0 0x0 0x0 0x0>; 137 reg-shift = <0>; 138 clock-frequency = <1843200>; 139 current-speed = <115200>; 140 }; 141 142 pciuart2: uart@a,3 { 143 compatible = "pci8086,8813.00", 144 "pci8086,8813", 145 "pciclass,070002", 146 "pciclass,0700", 147 "x86-uart"; 148 u-boot,dm-pre-reloc; 149 reg = <0x00025300 0x0 0x0 0x0 0x0 150 0x01025310 0x0 0x0 0x0 0x0>; 151 reg-shift = <0>; 152 clock-frequency = <1843200>; 153 current-speed = <115200>; 154 }; 155 156 pciuart3: uart@a,4 { 157 compatible = "pci8086,8814.00", 158 "pci8086,8814", 159 "pciclass,070002", 160 "pciclass,0700", 161 "x86-uart"; 162 u-boot,dm-pre-reloc; 163 reg = <0x00025400 0x0 0x0 0x0 0x0 164 0x01025410 0x0 0x0 0x0 0x0>; 165 reg-shift = <0>; 166 clock-frequency = <1843200>; 167 current-speed = <115200>; 168 }; 169 }; 170 }; 171 172 irq-router@1f,0 { 173 reg = <0x0000f800 0 0 0 0>; 174 compatible = "intel,irq-router"; 175 intel,pirq-config = "pci"; 176 intel,pirq-link = <0x60 8>; 177 intel,pirq-mask = <0xcee0>; 178 intel,pirq-routing = < 179 /* TunnelCreek PCI devices */ 180 PCI_BDF(0, 2, 0) INTA PIRQE 181 PCI_BDF(0, 3, 0) INTA PIRQF 182 PCI_BDF(0, 23, 0) INTA PIRQA 183 PCI_BDF(0, 23, 0) INTB PIRQB 184 PCI_BDF(0, 23, 0) INTC PIRQC 185 PCI_BDF(0, 23, 0) INTD PIRQD 186 PCI_BDF(0, 24, 0) INTA PIRQB 187 PCI_BDF(0, 24, 0) INTB PIRQC 188 PCI_BDF(0, 24, 0) INTC PIRQD 189 PCI_BDF(0, 24, 0) INTD PIRQA 190 PCI_BDF(0, 25, 0) INTA PIRQC 191 PCI_BDF(0, 25, 0) INTB PIRQD 192 PCI_BDF(0, 25, 0) INTC PIRQA 193 PCI_BDF(0, 25, 0) INTD PIRQB 194 PCI_BDF(0, 26, 0) INTA PIRQD 195 PCI_BDF(0, 26, 0) INTB PIRQA 196 PCI_BDF(0, 26, 0) INTC PIRQB 197 PCI_BDF(0, 26, 0) INTD PIRQC 198 PCI_BDF(0, 27, 0) INTA PIRQG 199 /* 200 * Topcliff PCI devices 201 * 202 * Note on the Crown Bay board, Topcliff chipset 203 * is connected to TunnelCreek PCIe port 0, so 204 * its bus number is 1 for its PCIe port and 2 205 * for its PCI devices per U-Boot current PCI 206 * bus enumeration algorithm. 207 */ 208 PCI_BDF(1, 0, 0) INTA PIRQA 209 PCI_BDF(2, 0, 1) INTA PIRQA 210 PCI_BDF(2, 0, 2) INTA PIRQA 211 PCI_BDF(2, 2, 0) INTB PIRQD 212 PCI_BDF(2, 2, 1) INTB PIRQD 213 PCI_BDF(2, 2, 2) INTB PIRQD 214 PCI_BDF(2, 2, 3) INTB PIRQD 215 PCI_BDF(2, 2, 4) INTB PIRQD 216 PCI_BDF(2, 4, 0) INTC PIRQC 217 PCI_BDF(2, 4, 1) INTC PIRQC 218 PCI_BDF(2, 6, 0) INTD PIRQB 219 PCI_BDF(2, 8, 0) INTA PIRQA 220 PCI_BDF(2, 8, 1) INTA PIRQA 221 PCI_BDF(2, 8, 2) INTA PIRQA 222 PCI_BDF(2, 8, 3) INTA PIRQA 223 PCI_BDF(2, 10, 0) INTB PIRQD 224 PCI_BDF(2, 10, 1) INTB PIRQD 225 PCI_BDF(2, 10, 2) INTB PIRQD 226 PCI_BDF(2, 10, 3) INTB PIRQD 227 PCI_BDF(2, 10, 4) INTB PIRQD 228 PCI_BDF(2, 12, 0) INTC PIRQC 229 PCI_BDF(2, 12, 1) INTC PIRQC 230 PCI_BDF(2, 12, 2) INTC PIRQC 231 PCI_BDF(2, 12, 3) INTC PIRQC 232 PCI_BDF(2, 12, 4) INTC PIRQC 233 >; 234 }; 235 }; 236 237}; 238