1/* 2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/interrupt-router/intel-irq.h> 10 11/include/ "skeleton.dtsi" 12/include/ "serial.dtsi" 13 14/ { 15 model = "Intel Crown Bay"; 16 compatible = "intel,crownbay", "intel,queensbay"; 17 18 aliases { 19 spi0 = "/spi"; 20 }; 21 22 config { 23 silent_console = <0>; 24 }; 25 26 gpioa { 27 compatible = "intel,ich6-gpio"; 28 u-boot,dm-pre-reloc; 29 reg = <0 0x20>; 30 bank-name = "A"; 31 }; 32 33 gpiob { 34 compatible = "intel,ich6-gpio"; 35 u-boot,dm-pre-reloc; 36 reg = <0x20 0x20>; 37 bank-name = "B"; 38 }; 39 40 chosen { 41 /* 42 * By default the legacy superio serial port is used as the 43 * U-Boot serial console. If we want to use UART from Topcliff 44 * PCH as the console, change this property to &pciuart#. 45 * 46 * For example, stdout-path = &pciuart0 will use the first 47 * UART on Topcliff PCH. 48 */ 49 stdout-path = "/serial"; 50 }; 51 52 spi { 53 #address-cells = <1>; 54 #size-cells = <0>; 55 compatible = "intel,ich-spi"; 56 spi-flash@0 { 57 reg = <0>; 58 compatible = "sst,25vf016b", "spi-flash"; 59 memory-map = <0xffe00000 0x00200000>; 60 }; 61 }; 62 63 microcode { 64 update@0 { 65#include "microcode/m0220661105_cv.dtsi" 66 }; 67 }; 68 69 pci { 70 #address-cells = <3>; 71 #size-cells = <2>; 72 compatible = "intel,pci"; 73 device_type = "pci"; 74 75 pcie@17,0 { 76 #address-cells = <3>; 77 #size-cells = <2>; 78 compatible = "intel,pci"; 79 device_type = "pci"; 80 81 topcliff@0,0 { 82 #address-cells = <3>; 83 #size-cells = <2>; 84 compatible = "intel,pci"; 85 device_type = "pci"; 86 87 pciuart0: uart@a,1 { 88 compatible = "pci8086,8811.00", 89 "pci8086,8811", 90 "pciclass,070002", 91 "pciclass,0700", 92 "x86-uart"; 93 reg = <0x00025100 0x0 0x0 0x0 0x0 94 0x01025110 0x0 0x0 0x0 0x0>; 95 reg-shift = <0>; 96 clock-frequency = <1843200>; 97 current-speed = <115200>; 98 }; 99 100 pciuart1: uart@a,2 { 101 compatible = "pci8086,8812.00", 102 "pci8086,8812", 103 "pciclass,070002", 104 "pciclass,0700", 105 "x86-uart"; 106 reg = <0x00025200 0x0 0x0 0x0 0x0 107 0x01025210 0x0 0x0 0x0 0x0>; 108 reg-shift = <0>; 109 clock-frequency = <1843200>; 110 current-speed = <115200>; 111 }; 112 113 pciuart2: uart@a,3 { 114 compatible = "pci8086,8813.00", 115 "pci8086,8813", 116 "pciclass,070002", 117 "pciclass,0700", 118 "x86-uart"; 119 reg = <0x00025300 0x0 0x0 0x0 0x0 120 0x01025310 0x0 0x0 0x0 0x0>; 121 reg-shift = <0>; 122 clock-frequency = <1843200>; 123 current-speed = <115200>; 124 }; 125 126 pciuart3: uart@a,4 { 127 compatible = "pci8086,8814.00", 128 "pci8086,8814", 129 "pciclass,070002", 130 "pciclass,0700", 131 "x86-uart"; 132 reg = <0x00025400 0x0 0x0 0x0 0x0 133 0x01025410 0x0 0x0 0x0 0x0>; 134 reg-shift = <0>; 135 clock-frequency = <1843200>; 136 current-speed = <115200>; 137 }; 138 }; 139 }; 140 141 irq-router@1f,0 { 142 reg = <0x0000f800 0 0 0 0>; 143 compatible = "intel,irq-router"; 144 intel,pirq-config = "pci"; 145 intel,pirq-link = <0x60 8>; 146 intel,pirq-mask = <0xdee0>; 147 intel,pirq-routing = < 148 /* TunnelCreek PCI devices */ 149 PCI_BDF(0, 2, 0) INTA PIRQE 150 PCI_BDF(0, 3, 0) INTA PIRQF 151 PCI_BDF(0, 23, 0) INTA PIRQE 152 PCI_BDF(0, 24, 0) INTA PIRQF 153 PCI_BDF(0, 25, 0) INTA PIRQG 154 PCI_BDF(0, 26, 0) INTA PIRQH 155 PCI_BDF(0, 27, 0) INTA PIRQG 156 /* 157 * Topcliff PCI devices 158 * 159 * Note on the Crown Bay board, Topcliff chipset 160 * is connected to TunnelCreek PCIe port 0, so 161 * its bus number is 1 for its PCIe port and 2 162 * for its PCI devices per U-Boot currnet PCI 163 * bus enumeration algorithm. 164 */ 165 PCI_BDF(1, 0, 0) INTA PIRQA 166 PCI_BDF(2, 0, 1) INTA PIRQA 167 PCI_BDF(2, 0, 2) INTA PIRQA 168 PCI_BDF(2, 2, 0) INTB PIRQB 169 PCI_BDF(2, 2, 1) INTB PIRQB 170 PCI_BDF(2, 2, 2) INTB PIRQB 171 PCI_BDF(2, 2, 3) INTB PIRQB 172 PCI_BDF(2, 2, 4) INTB PIRQB 173 PCI_BDF(2, 4, 0) INTC PIRQC 174 PCI_BDF(2, 4, 1) INTC PIRQC 175 PCI_BDF(2, 6, 0) INTD PIRQD 176 PCI_BDF(2, 8, 0) INTA PIRQA 177 PCI_BDF(2, 8, 1) INTA PIRQA 178 PCI_BDF(2, 8, 2) INTA PIRQA 179 PCI_BDF(2, 8, 3) INTA PIRQA 180 PCI_BDF(2, 10, 0) INTB PIRQB 181 PCI_BDF(2, 10, 1) INTB PIRQB 182 PCI_BDF(2, 10, 2) INTB PIRQB 183 PCI_BDF(2, 10, 3) INTB PIRQB 184 PCI_BDF(2, 10, 4) INTB PIRQB 185 PCI_BDF(2, 12, 0) INTC PIRQC 186 PCI_BDF(2, 12, 1) INTC PIRQC 187 PCI_BDF(2, 12, 2) INTC PIRQC 188 PCI_BDF(2, 12, 3) INTC PIRQC 189 PCI_BDF(2, 12, 4) INTC PIRQC 190 >; 191 }; 192 }; 193 194}; 195