1/* 2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/interrupt-router/intel-irq.h> 10 11/include/ "skeleton.dtsi" 12/include/ "serial.dtsi" 13/include/ "keyboard.dtsi" 14/include/ "rtc.dtsi" 15/include/ "tsc_timer.dtsi" 16 17/ { 18 model = "Intel Crown Bay"; 19 compatible = "intel,crownbay", "intel,queensbay"; 20 21 aliases { 22 spi0 = "/spi"; 23 }; 24 25 config { 26 silent_console = <0>; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu@0 { 34 device_type = "cpu"; 35 compatible = "cpu-x86"; 36 reg = <0>; 37 intel,apic-id = <0>; 38 }; 39 40 cpu@1 { 41 device_type = "cpu"; 42 compatible = "cpu-x86"; 43 reg = <1>; 44 intel,apic-id = <1>; 45 }; 46 47 }; 48 49 gpioa { 50 compatible = "intel,ich6-gpio"; 51 u-boot,dm-pre-reloc; 52 reg = <0 0x20>; 53 bank-name = "A"; 54 }; 55 56 gpiob { 57 compatible = "intel,ich6-gpio"; 58 u-boot,dm-pre-reloc; 59 reg = <0x20 0x20>; 60 bank-name = "B"; 61 }; 62 63 chosen { 64 /* 65 * By default the legacy superio serial port is used as the 66 * U-Boot serial console. If we want to use UART from Topcliff 67 * PCH as the console, change this property to &pciuart#. 68 * 69 * For example, stdout-path = &pciuart0 will use the first 70 * UART on Topcliff PCH. 71 */ 72 stdout-path = "/serial"; 73 }; 74 75 spi { 76 #address-cells = <1>; 77 #size-cells = <0>; 78 compatible = "intel,ich-spi"; 79 spi-flash@0 { 80 reg = <0>; 81 compatible = "sst,25vf016b", "spi-flash"; 82 memory-map = <0xffe00000 0x00200000>; 83 }; 84 }; 85 86 microcode { 87 update@0 { 88#include "microcode/m0220661105_cv.dtsi" 89 }; 90 }; 91 92 pci { 93 #address-cells = <3>; 94 #size-cells = <2>; 95 compatible = "pci-x86"; 96 u-boot,dm-pre-reloc; 97 ranges = <0x02000000 0x0 0x40000000 0x40000000 0 0x80000000 98 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 99 0x01000000 0x0 0x2000 0x2000 0 0xe000>; 100 101 pcie@17,0 { 102 #address-cells = <3>; 103 #size-cells = <2>; 104 compatible = "pci-bridge"; 105 u-boot,dm-pre-reloc; 106 reg = <0x0000b800 0x0 0x0 0x0 0x0>; 107 108 topcliff@0,0 { 109 #address-cells = <3>; 110 #size-cells = <2>; 111 compatible = "pci-bridge"; 112 u-boot,dm-pre-reloc; 113 reg = <0x00010000 0x0 0x0 0x0 0x0>; 114 115 pciuart0: uart@a,1 { 116 compatible = "pci8086,8811.00", 117 "pci8086,8811", 118 "pciclass,070002", 119 "pciclass,0700", 120 "ns16550"; 121 u-boot,dm-pre-reloc; 122 reg = <0x00025100 0x0 0x0 0x0 0x0 123 0x01025110 0x0 0x0 0x0 0x0>; 124 reg-shift = <0>; 125 clock-frequency = <1843200>; 126 current-speed = <115200>; 127 }; 128 129 pciuart1: uart@a,2 { 130 compatible = "pci8086,8812.00", 131 "pci8086,8812", 132 "pciclass,070002", 133 "pciclass,0700", 134 "ns16550"; 135 u-boot,dm-pre-reloc; 136 reg = <0x00025200 0x0 0x0 0x0 0x0 137 0x01025210 0x0 0x0 0x0 0x0>; 138 reg-shift = <0>; 139 clock-frequency = <1843200>; 140 current-speed = <115200>; 141 }; 142 143 pciuart2: uart@a,3 { 144 compatible = "pci8086,8813.00", 145 "pci8086,8813", 146 "pciclass,070002", 147 "pciclass,0700", 148 "ns16550"; 149 u-boot,dm-pre-reloc; 150 reg = <0x00025300 0x0 0x0 0x0 0x0 151 0x01025310 0x0 0x0 0x0 0x0>; 152 reg-shift = <0>; 153 clock-frequency = <1843200>; 154 current-speed = <115200>; 155 }; 156 157 pciuart3: uart@a,4 { 158 compatible = "pci8086,8814.00", 159 "pci8086,8814", 160 "pciclass,070002", 161 "pciclass,0700", 162 "ns16550"; 163 u-boot,dm-pre-reloc; 164 reg = <0x00025400 0x0 0x0 0x0 0x0 165 0x01025410 0x0 0x0 0x0 0x0>; 166 reg-shift = <0>; 167 clock-frequency = <1843200>; 168 current-speed = <115200>; 169 }; 170 }; 171 }; 172 173 irq-router@1f,0 { 174 reg = <0x0000f800 0 0 0 0>; 175 compatible = "intel,irq-router"; 176 intel,pirq-config = "pci"; 177 intel,pirq-link = <0x60 8>; 178 intel,pirq-mask = <0xcee0>; 179 intel,pirq-routing = < 180 /* TunnelCreek PCI devices */ 181 PCI_BDF(0, 2, 0) INTA PIRQE 182 PCI_BDF(0, 3, 0) INTA PIRQF 183 PCI_BDF(0, 23, 0) INTA PIRQA 184 PCI_BDF(0, 23, 0) INTB PIRQB 185 PCI_BDF(0, 23, 0) INTC PIRQC 186 PCI_BDF(0, 23, 0) INTD PIRQD 187 PCI_BDF(0, 24, 0) INTA PIRQB 188 PCI_BDF(0, 24, 0) INTB PIRQC 189 PCI_BDF(0, 24, 0) INTC PIRQD 190 PCI_BDF(0, 24, 0) INTD PIRQA 191 PCI_BDF(0, 25, 0) INTA PIRQC 192 PCI_BDF(0, 25, 0) INTB PIRQD 193 PCI_BDF(0, 25, 0) INTC PIRQA 194 PCI_BDF(0, 25, 0) INTD PIRQB 195 PCI_BDF(0, 26, 0) INTA PIRQD 196 PCI_BDF(0, 26, 0) INTB PIRQA 197 PCI_BDF(0, 26, 0) INTC PIRQB 198 PCI_BDF(0, 26, 0) INTD PIRQC 199 PCI_BDF(0, 27, 0) INTA PIRQG 200 /* 201 * Topcliff PCI devices 202 * 203 * Note on the Crown Bay board, Topcliff chipset 204 * is connected to TunnelCreek PCIe port 0, so 205 * its bus number is 1 for its PCIe port and 2 206 * for its PCI devices per U-Boot current PCI 207 * bus enumeration algorithm. 208 */ 209 PCI_BDF(1, 0, 0) INTA PIRQA 210 PCI_BDF(2, 0, 1) INTA PIRQA 211 PCI_BDF(2, 0, 2) INTA PIRQA 212 PCI_BDF(2, 2, 0) INTB PIRQD 213 PCI_BDF(2, 2, 1) INTB PIRQD 214 PCI_BDF(2, 2, 2) INTB PIRQD 215 PCI_BDF(2, 2, 3) INTB PIRQD 216 PCI_BDF(2, 2, 4) INTB PIRQD 217 PCI_BDF(2, 4, 0) INTC PIRQC 218 PCI_BDF(2, 4, 1) INTC PIRQC 219 PCI_BDF(2, 6, 0) INTD PIRQB 220 PCI_BDF(2, 8, 0) INTA PIRQA 221 PCI_BDF(2, 8, 1) INTA PIRQA 222 PCI_BDF(2, 8, 2) INTA PIRQA 223 PCI_BDF(2, 8, 3) INTA PIRQA 224 PCI_BDF(2, 10, 0) INTB PIRQD 225 PCI_BDF(2, 10, 1) INTB PIRQD 226 PCI_BDF(2, 10, 2) INTB PIRQD 227 PCI_BDF(2, 10, 3) INTB PIRQD 228 PCI_BDF(2, 10, 4) INTB PIRQD 229 PCI_BDF(2, 12, 0) INTC PIRQC 230 PCI_BDF(2, 12, 1) INTC PIRQC 231 PCI_BDF(2, 12, 2) INTC PIRQC 232 PCI_BDF(2, 12, 3) INTC PIRQC 233 PCI_BDF(2, 12, 4) INTC PIRQC 234 >; 235 }; 236 }; 237 238}; 239