1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/interrupt-router/intel-irq.h> 9 10/include/ "skeleton.dtsi" 11/include/ "serial.dtsi" 12/include/ "keyboard.dtsi" 13/include/ "rtc.dtsi" 14/include/ "tsc_timer.dtsi" 15 16/ { 17 model = "Intel Cougar Canyon 2"; 18 compatible = "intel,cougarcanyon2", "intel,chiefriver"; 19 20 aliases { 21 spi0 = &spi0; 22 }; 23 24 config { 25 silent_console = <0>; 26 }; 27 28 chosen { 29 stdout-path = "/serial"; 30 }; 31 32 cpus { 33 #address-cells = <1>; 34 #size-cells = <0>; 35 36 cpu@0 { 37 device_type = "cpu"; 38 compatible = "intel,core-gen3"; 39 reg = <0>; 40 intel,apic-id = <0>; 41 }; 42 43 cpu@1 { 44 device_type = "cpu"; 45 compatible = "intel,core-gen3"; 46 reg = <1>; 47 intel,apic-id = <1>; 48 }; 49 50 cpu@2 { 51 device_type = "cpu"; 52 compatible = "intel,core-gen3"; 53 reg = <2>; 54 intel,apic-id = <2>; 55 }; 56 57 cpu@3 { 58 device_type = "cpu"; 59 compatible = "intel,core-gen3"; 60 reg = <3>; 61 intel,apic-id = <3>; 62 }; 63 }; 64 65 microcode { 66 update@0 { 67#include "microcode/m12306a2_00000008.dtsi" 68 }; 69 update@1 { 70#include "microcode/m12306a4_00000007.dtsi" 71 }; 72 update@2 { 73#include "microcode/m12306a5_00000007.dtsi" 74 }; 75 update@3 { 76#include "microcode/m12306a8_00000010.dtsi" 77 }; 78 update@4 { 79#include "microcode/m12306a9_0000001b.dtsi" 80 }; 81 }; 82 83 fsp { 84 compatible = "intel,ivybridge-fsp"; 85 fsp,enable-ht; 86 }; 87 88 pci { 89 #address-cells = <3>; 90 #size-cells = <2>; 91 compatible = "pci-x86"; 92 u-boot,dm-pre-reloc; 93 ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000 94 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000 95 0x01000000 0x0 0x2000 0x2000 0 0xe000>; 96 97 pch@1f,0 { 98 reg = <0x0000f800 0 0 0 0>; 99 compatible = "intel,bd82x6x"; 100 u-boot,dm-pre-reloc; 101 #address-cells = <1>; 102 #size-cells = <1>; 103 104 irq-router { 105 compatible = "intel,irq-router"; 106 intel,pirq-config = "pci"; 107 intel,actl-8bit; 108 intel,actl-addr = <0x44>; 109 intel,pirq-link = <0x60 8>; 110 intel,pirq-regmap = < 111 PIRQA 0 112 PIRQB 1 113 PIRQC 2 114 PIRQD 3 115 PIRQE 8 116 PIRQF 9 117 PIRQG 10 118 PIRQH 11 119 >; 120 intel,pirq-mask = <0xcee0>; 121 intel,pirq-routing = < 122 /* Panther Point PCI devices */ 123 PCI_BDF(0, 2, 0) INTA PIRQA 124 PCI_BDF(0, 20, 0) INTA PIRQA 125 PCI_BDF(0, 22, 0) INTA PIRQA 126 PCI_BDF(0, 22, 1) INTB PIRQB 127 PCI_BDF(0, 22, 2) INTC PIRQC 128 PCI_BDF(0, 22, 3) INTD PIRQD 129 PCI_BDF(0, 25, 0) INTA PIRQA 130 PCI_BDF(0, 26, 0) INTA PIRQA 131 PCI_BDF(0, 27, 0) INTB PIRQA 132 PCI_BDF(0, 28, 0) INTA PIRQA 133 PCI_BDF(0, 28, 1) INTB PIRQB 134 PCI_BDF(0, 28, 2) INTC PIRQC 135 PCI_BDF(0, 28, 3) INTD PIRQD 136 PCI_BDF(0, 28, 4) INTA PIRQA 137 PCI_BDF(0, 28, 5) INTB PIRQB 138 PCI_BDF(0, 28, 6) INTC PIRQC 139 PCI_BDF(0, 28, 7) INTD PIRQD 140 PCI_BDF(0, 29, 0) INTA PIRQA 141 PCI_BDF(0, 31, 2) INTB PIRQB 142 PCI_BDF(0, 31, 3) INTC PIRQC 143 PCI_BDF(0, 31, 5) INTB PIRQB 144 PCI_BDF(0, 31, 6) INTC PIRQC 145 >; 146 }; 147 148 spi0: spi { 149 #address-cells = <1>; 150 #size-cells = <0>; 151 compatible = "intel,ich9-spi"; 152 intel,spi-lock-down; 153 154 spi-flash@0 { 155 reg = <0>; 156 compatible = "winbond,w25q64bv", "spi-flash"; 157 memory-map = <0xff800000 0x00800000>; 158 }; 159 }; 160 161 gpioa { 162 compatible = "intel,ich6-gpio"; 163 u-boot,dm-pre-reloc; 164 reg = <0 0x10>; 165 bank-name = "A"; 166 }; 167 168 gpiob { 169 compatible = "intel,ich6-gpio"; 170 u-boot,dm-pre-reloc; 171 reg = <0x30 0x10>; 172 bank-name = "B"; 173 }; 174 175 gpioc { 176 compatible = "intel,ich6-gpio"; 177 u-boot,dm-pre-reloc; 178 reg = <0x40 0x10>; 179 bank-name = "C"; 180 }; 181 }; 182 }; 183 184}; 185