1/* 2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> 3 * Copyright (C) 2016 Stefan Roese <sr@denx.de> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/dts-v1/; 9 10#include <dt-bindings/gpio/x86-gpio.h> 11#include <dt-bindings/interrupt-router/intel-irq.h> 12 13/include/ "skeleton.dtsi" 14/include/ "serial.dtsi" 15/include/ "rtc.dtsi" 16/include/ "tsc_timer.dtsi" 17 18/ { 19 model = "congatec-QEVAL20-QA3-E3845"; 20 compatible = "congatec,qeval20-qa3-e3845", "intel,baytrail"; 21 22 aliases { 23 serial0 = &serial; 24 spi0 = &spi; 25 }; 26 27 config { 28 silent_console = <0>; 29 }; 30 31 pch_pinctrl { 32 compatible = "intel,x86-pinctrl"; 33 }; 34 35 chosen { 36 stdout-path = "/serial"; 37 }; 38 39 cpus { 40 #address-cells = <1>; 41 #size-cells = <0>; 42 43 cpu@0 { 44 device_type = "cpu"; 45 compatible = "intel,baytrail-cpu"; 46 reg = <0>; 47 intel,apic-id = <0>; 48 }; 49 50 cpu@1 { 51 device_type = "cpu"; 52 compatible = "intel,baytrail-cpu"; 53 reg = <1>; 54 intel,apic-id = <2>; 55 }; 56 57 cpu@2 { 58 device_type = "cpu"; 59 compatible = "intel,baytrail-cpu"; 60 reg = <2>; 61 intel,apic-id = <4>; 62 }; 63 64 cpu@3 { 65 device_type = "cpu"; 66 compatible = "intel,baytrail-cpu"; 67 reg = <3>; 68 intel,apic-id = <6>; 69 }; 70 }; 71 72 pci { 73 compatible = "intel,pci-baytrail", "pci-x86"; 74 #address-cells = <3>; 75 #size-cells = <2>; 76 u-boot,dm-pre-reloc; 77 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000 78 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 79 0x01000000 0x0 0x2000 0x2000 0 0xe000>; 80 81 pch@1f,0 { 82 reg = <0x0000f800 0 0 0 0>; 83 compatible = "pci8086,0f1c", "intel,pch9"; 84 #address-cells = <1>; 85 #size-cells = <1>; 86 87 irq-router { 88 compatible = "intel,irq-router"; 89 intel,pirq-config = "ibase"; 90 intel,ibase-offset = <0x50>; 91 intel,pirq-link = <8 8>; 92 intel,pirq-mask = <0xdee0>; 93 intel,pirq-routing = < 94 /* BayTrail PCI devices */ 95 PCI_BDF(0, 2, 0) INTA PIRQA 96 PCI_BDF(0, 3, 0) INTA PIRQA 97 PCI_BDF(0, 16, 0) INTA PIRQA 98 PCI_BDF(0, 17, 0) INTA PIRQA 99 PCI_BDF(0, 18, 0) INTA PIRQA 100 PCI_BDF(0, 19, 0) INTA PIRQA 101 PCI_BDF(0, 20, 0) INTA PIRQA 102 PCI_BDF(0, 21, 0) INTA PIRQA 103 PCI_BDF(0, 22, 0) INTA PIRQA 104 PCI_BDF(0, 23, 0) INTA PIRQA 105 PCI_BDF(0, 24, 0) INTA PIRQA 106 PCI_BDF(0, 24, 1) INTC PIRQC 107 PCI_BDF(0, 24, 2) INTD PIRQD 108 PCI_BDF(0, 24, 3) INTB PIRQB 109 PCI_BDF(0, 24, 4) INTA PIRQA 110 PCI_BDF(0, 24, 5) INTC PIRQC 111 PCI_BDF(0, 24, 6) INTD PIRQD 112 PCI_BDF(0, 24, 7) INTB PIRQB 113 PCI_BDF(0, 26, 0) INTA PIRQA 114 PCI_BDF(0, 27, 0) INTA PIRQA 115 PCI_BDF(0, 28, 0) INTA PIRQA 116 PCI_BDF(0, 28, 1) INTB PIRQB 117 PCI_BDF(0, 28, 2) INTC PIRQC 118 PCI_BDF(0, 28, 3) INTD PIRQD 119 PCI_BDF(0, 29, 0) INTA PIRQA 120 PCI_BDF(0, 30, 0) INTA PIRQA 121 PCI_BDF(0, 30, 1) INTD PIRQD 122 PCI_BDF(0, 30, 2) INTB PIRQB 123 PCI_BDF(0, 30, 3) INTC PIRQC 124 PCI_BDF(0, 30, 4) INTD PIRQD 125 PCI_BDF(0, 30, 5) INTB PIRQB 126 PCI_BDF(0, 31, 3) INTB PIRQB 127 128 /* 129 * PCIe root ports downstream 130 * interrupts 131 */ 132 PCI_BDF(1, 0, 0) INTA PIRQA 133 PCI_BDF(1, 0, 0) INTB PIRQB 134 PCI_BDF(1, 0, 0) INTC PIRQC 135 PCI_BDF(1, 0, 0) INTD PIRQD 136 PCI_BDF(2, 0, 0) INTA PIRQB 137 PCI_BDF(2, 0, 0) INTB PIRQC 138 PCI_BDF(2, 0, 0) INTC PIRQD 139 PCI_BDF(2, 0, 0) INTD PIRQA 140 PCI_BDF(3, 0, 0) INTA PIRQC 141 PCI_BDF(3, 0, 0) INTB PIRQD 142 PCI_BDF(3, 0, 0) INTC PIRQA 143 PCI_BDF(3, 0, 0) INTD PIRQB 144 PCI_BDF(4, 0, 0) INTA PIRQD 145 PCI_BDF(4, 0, 0) INTB PIRQA 146 PCI_BDF(4, 0, 0) INTC PIRQB 147 PCI_BDF(4, 0, 0) INTD PIRQC 148 >; 149 }; 150 151 spi: spi { 152 #address-cells = <1>; 153 #size-cells = <0>; 154 compatible = "intel,ich9-spi"; 155 spi-flash@0 { 156 #address-cells = <1>; 157 #size-cells = <1>; 158 reg = <0>; 159 compatible = "stmicro,n25q064a", 160 "spi-flash"; 161 memory-map = <0xff800000 0x00800000>; 162 rw-mrc-cache { 163 label = "rw-mrc-cache"; 164 reg = <0x006f0000 0x00010000>; 165 }; 166 }; 167 }; 168 169 gpioa { 170 compatible = "intel,ich6-gpio"; 171 u-boot,dm-pre-reloc; 172 reg = <0 0x20>; 173 bank-name = "A"; 174 }; 175 176 gpiob { 177 compatible = "intel,ich6-gpio"; 178 u-boot,dm-pre-reloc; 179 reg = <0x20 0x20>; 180 bank-name = "B"; 181 }; 182 183 gpioc { 184 compatible = "intel,ich6-gpio"; 185 u-boot,dm-pre-reloc; 186 reg = <0x40 0x20>; 187 bank-name = "C"; 188 }; 189 190 gpiod { 191 compatible = "intel,ich6-gpio"; 192 u-boot,dm-pre-reloc; 193 reg = <0x60 0x20>; 194 bank-name = "D"; 195 }; 196 197 gpioe { 198 compatible = "intel,ich6-gpio"; 199 u-boot,dm-pre-reloc; 200 reg = <0x80 0x20>; 201 bank-name = "E"; 202 }; 203 204 gpiof { 205 compatible = "intel,ich6-gpio"; 206 u-boot,dm-pre-reloc; 207 reg = <0xA0 0x20>; 208 bank-name = "F"; 209 }; 210 }; 211 }; 212 213 fsp { 214 compatible = "intel,baytrail-fsp"; 215 fsp,mrc-init-tseg-size = <0>; 216 fsp,mrc-init-mmio-size = <0x800>; 217 fsp,mrc-init-spd-addr1 = <0xa0>; 218 fsp,mrc-init-spd-addr2 = <0xa2>; 219 fsp,emmc-boot-mode = <2>; 220 fsp,enable-sdio; 221 fsp,enable-sdcard; 222 fsp,enable-hsuart1; 223 fsp,enable-spi; 224 fsp,enable-sata; 225 fsp,sata-mode = <1>; 226 fsp,enable-lpe; 227 fsp,lpss-sio-enable-pci-mode; 228 fsp,enable-dma0; 229 fsp,enable-dma1; 230 fsp,enable-i2c0; 231 fsp,enable-i2c1; 232 fsp,enable-i2c2; 233 fsp,enable-i2c3; 234 fsp,enable-i2c4; 235 fsp,enable-i2c5; 236 fsp,enable-i2c6; 237 fsp,enable-pwm0; 238 fsp,enable-pwm1; 239 fsp,igd-dvmt50-pre-alloc = <2>; 240 fsp,aperture-size = <2>; 241 fsp,gtt-size = <2>; 242 fsp,scc-enable-pci-mode; 243 fsp,os-selection = <4>; 244 fsp,emmc45-ddr50-enabled; 245 fsp,emmc45-retune-timer-value = <8>; 246 fsp,enable-igd; 247 fsp,enable-memory-down; 248 fsp,memory-down-params { 249 compatible = "intel,baytrail-fsp-mdp"; 250 fsp,dram-speed = <2>; /* 2=1333MHz */ 251 fsp,dram-type = <1>; /* 1=DDR3L */ 252 fsp,dimm-0-enable; 253 fsp,dimm-1-enable; 254 fsp,dimm-width = <1>; /* 1=x16, 2=x32 */ 255 fsp,dimm-density = <2>; /* 2=4Gbit */ 256 fsp,dimm-bus-width = <3>; /* 3=64bits */ 257 fsp,dimm-sides = <0>; /* 0=1 ranks -> 0x2b */ 258 259 /* These following values might need a re-visit */ 260 fsp,dimm-tcl = <8>; 261 fsp,dimm-trpt-rcd = <8>; 262 fsp,dimm-twr = <8>; 263 fsp,dimm-twtr = <4>; 264 fsp,dimm-trrd = <6>; 265 fsp,dimm-trtp = <4>; 266 fsp,dimm-tfaw = <22>; 267 }; 268 }; 269 270 microcode { 271 update@0 { 272#include "microcode/m0130673322.dtsi" 273 }; 274 update@1 { 275#include "microcode/m0130679901.dtsi" 276 }; 277 }; 278}; 279