1/* 2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> 3 * Copyright (C) 2016 Stefan Roese <sr@denx.de> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/dts-v1/; 9 10#include <dt-bindings/gpio/x86-gpio.h> 11#include <dt-bindings/interrupt-router/intel-irq.h> 12 13/include/ "skeleton.dtsi" 14/include/ "serial.dtsi" 15/include/ "rtc.dtsi" 16/include/ "tsc_timer.dtsi" 17 18/ { 19 model = "congatec-QEVAL20-QA3-E3845"; 20 compatible = "congatec,qeval20-qa3-e3845", "intel,baytrail"; 21 22 aliases { 23 serial0 = &serial; 24 spi0 = &spi; 25 }; 26 27 config { 28 silent_console = <0>; 29 }; 30 31 pch_pinctrl { 32 compatible = "intel,x86-pinctrl"; 33 reg = <0 0>; 34 35 /* 36 * As of today, the latest version FSP (gold4) for BayTrail 37 * misses the PAD configuration of the SD controller's Card 38 * Detect signal. The default PAD value for the CD pin sets 39 * the pin to work in GPIO mode, which causes card detect 40 * status cannot be reflected by the Present State register 41 * in the SD controller (bit 16 & bit 18 are always zero). 42 * 43 * Configure this pin to function 1 (SD controller). 44 */ 45 sdmmc3_cd@0 { 46 pad-offset = <0x3a0>; 47 mode-func = <1>; 48 }; 49 }; 50 51 chosen { 52 stdout-path = "/serial"; 53 }; 54 55 cpus { 56 #address-cells = <1>; 57 #size-cells = <0>; 58 59 cpu@0 { 60 device_type = "cpu"; 61 compatible = "intel,baytrail-cpu"; 62 reg = <0>; 63 intel,apic-id = <0>; 64 }; 65 66 cpu@1 { 67 device_type = "cpu"; 68 compatible = "intel,baytrail-cpu"; 69 reg = <1>; 70 intel,apic-id = <2>; 71 }; 72 73 cpu@2 { 74 device_type = "cpu"; 75 compatible = "intel,baytrail-cpu"; 76 reg = <2>; 77 intel,apic-id = <4>; 78 }; 79 80 cpu@3 { 81 device_type = "cpu"; 82 compatible = "intel,baytrail-cpu"; 83 reg = <3>; 84 intel,apic-id = <6>; 85 }; 86 }; 87 88 pci { 89 compatible = "intel,pci-baytrail", "pci-x86"; 90 #address-cells = <3>; 91 #size-cells = <2>; 92 u-boot,dm-pre-reloc; 93 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000 94 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 95 0x01000000 0x0 0x2000 0x2000 0 0xe000>; 96 97 pch@1f,0 { 98 reg = <0x0000f800 0 0 0 0>; 99 compatible = "pci8086,0f1c", "intel,pch9"; 100 #address-cells = <1>; 101 #size-cells = <1>; 102 103 irq-router { 104 compatible = "intel,irq-router"; 105 intel,pirq-config = "ibase"; 106 intel,ibase-offset = <0x50>; 107 intel,actl-addr = <0>; 108 intel,pirq-link = <8 8>; 109 intel,pirq-mask = <0xdee0>; 110 intel,pirq-routing = < 111 /* BayTrail PCI devices */ 112 PCI_BDF(0, 2, 0) INTA PIRQA 113 PCI_BDF(0, 3, 0) INTA PIRQA 114 PCI_BDF(0, 16, 0) INTA PIRQA 115 PCI_BDF(0, 17, 0) INTA PIRQA 116 PCI_BDF(0, 18, 0) INTA PIRQA 117 PCI_BDF(0, 19, 0) INTA PIRQA 118 PCI_BDF(0, 20, 0) INTA PIRQA 119 PCI_BDF(0, 21, 0) INTA PIRQA 120 PCI_BDF(0, 22, 0) INTA PIRQA 121 PCI_BDF(0, 23, 0) INTA PIRQA 122 PCI_BDF(0, 24, 0) INTA PIRQA 123 PCI_BDF(0, 24, 1) INTC PIRQC 124 PCI_BDF(0, 24, 2) INTD PIRQD 125 PCI_BDF(0, 24, 3) INTB PIRQB 126 PCI_BDF(0, 24, 4) INTA PIRQA 127 PCI_BDF(0, 24, 5) INTC PIRQC 128 PCI_BDF(0, 24, 6) INTD PIRQD 129 PCI_BDF(0, 24, 7) INTB PIRQB 130 PCI_BDF(0, 26, 0) INTA PIRQA 131 PCI_BDF(0, 27, 0) INTA PIRQA 132 PCI_BDF(0, 28, 0) INTA PIRQA 133 PCI_BDF(0, 28, 1) INTB PIRQB 134 PCI_BDF(0, 28, 2) INTC PIRQC 135 PCI_BDF(0, 28, 3) INTD PIRQD 136 PCI_BDF(0, 29, 0) INTA PIRQA 137 PCI_BDF(0, 30, 0) INTA PIRQA 138 PCI_BDF(0, 30, 1) INTD PIRQD 139 PCI_BDF(0, 30, 2) INTB PIRQB 140 PCI_BDF(0, 30, 3) INTC PIRQC 141 PCI_BDF(0, 30, 4) INTD PIRQD 142 PCI_BDF(0, 30, 5) INTB PIRQB 143 PCI_BDF(0, 31, 3) INTB PIRQB 144 145 /* 146 * PCIe root ports downstream 147 * interrupts 148 */ 149 PCI_BDF(1, 0, 0) INTA PIRQA 150 PCI_BDF(1, 0, 0) INTB PIRQB 151 PCI_BDF(1, 0, 0) INTC PIRQC 152 PCI_BDF(1, 0, 0) INTD PIRQD 153 PCI_BDF(2, 0, 0) INTA PIRQB 154 PCI_BDF(2, 0, 0) INTB PIRQC 155 PCI_BDF(2, 0, 0) INTC PIRQD 156 PCI_BDF(2, 0, 0) INTD PIRQA 157 PCI_BDF(3, 0, 0) INTA PIRQC 158 PCI_BDF(3, 0, 0) INTB PIRQD 159 PCI_BDF(3, 0, 0) INTC PIRQA 160 PCI_BDF(3, 0, 0) INTD PIRQB 161 PCI_BDF(4, 0, 0) INTA PIRQD 162 PCI_BDF(4, 0, 0) INTB PIRQA 163 PCI_BDF(4, 0, 0) INTC PIRQB 164 PCI_BDF(4, 0, 0) INTD PIRQC 165 >; 166 }; 167 168 spi: spi { 169 #address-cells = <1>; 170 #size-cells = <0>; 171 compatible = "intel,ich9-spi"; 172 spi-flash@0 { 173 #address-cells = <1>; 174 #size-cells = <1>; 175 reg = <0>; 176 compatible = "stmicro,n25q064a", 177 "spi-flash"; 178 memory-map = <0xff800000 0x00800000>; 179 rw-mrc-cache { 180 label = "rw-mrc-cache"; 181 reg = <0x006f0000 0x00010000>; 182 }; 183 }; 184 }; 185 186 gpioa { 187 compatible = "intel,ich6-gpio"; 188 u-boot,dm-pre-reloc; 189 reg = <0 0x20>; 190 bank-name = "A"; 191 }; 192 193 gpiob { 194 compatible = "intel,ich6-gpio"; 195 u-boot,dm-pre-reloc; 196 reg = <0x20 0x20>; 197 bank-name = "B"; 198 }; 199 200 gpioc { 201 compatible = "intel,ich6-gpio"; 202 u-boot,dm-pre-reloc; 203 reg = <0x40 0x20>; 204 bank-name = "C"; 205 }; 206 207 gpiod { 208 compatible = "intel,ich6-gpio"; 209 u-boot,dm-pre-reloc; 210 reg = <0x60 0x20>; 211 bank-name = "D"; 212 }; 213 214 gpioe { 215 compatible = "intel,ich6-gpio"; 216 u-boot,dm-pre-reloc; 217 reg = <0x80 0x20>; 218 bank-name = "E"; 219 }; 220 221 gpiof { 222 compatible = "intel,ich6-gpio"; 223 u-boot,dm-pre-reloc; 224 reg = <0xA0 0x20>; 225 bank-name = "F"; 226 }; 227 }; 228 }; 229 230 fsp { 231 compatible = "intel,baytrail-fsp"; 232 fsp,mrc-init-tseg-size = <0>; 233 fsp,mrc-init-mmio-size = <0x800>; 234 fsp,mrc-init-spd-addr1 = <0xa0>; 235 fsp,mrc-init-spd-addr2 = <0xa2>; 236 fsp,emmc-boot-mode = <1>; 237 fsp,enable-sdio; 238 fsp,enable-sdcard; 239 fsp,enable-hsuart1; 240 fsp,enable-spi; 241 fsp,enable-sata; 242 fsp,sata-mode = <1>; 243 fsp,enable-lpe; 244 fsp,lpss-sio-enable-pci-mode; 245 fsp,enable-dma0; 246 fsp,enable-dma1; 247 fsp,enable-i2c0; 248 fsp,enable-i2c1; 249 fsp,enable-i2c2; 250 fsp,enable-i2c3; 251 fsp,enable-i2c4; 252 fsp,enable-i2c5; 253 fsp,enable-i2c6; 254 fsp,enable-pwm0; 255 fsp,enable-pwm1; 256 fsp,igd-dvmt50-pre-alloc = <2>; 257 fsp,aperture-size = <2>; 258 fsp,gtt-size = <2>; 259 fsp,scc-enable-pci-mode; 260 fsp,os-selection = <4>; 261 fsp,emmc45-ddr50-enabled; 262 fsp,emmc45-retune-timer-value = <8>; 263 fsp,enable-igd; 264 fsp,enable-memory-down; 265 fsp,memory-down-params { 266 compatible = "intel,baytrail-fsp-mdp"; 267 fsp,dram-speed = <2>; /* 2=1333MHz */ 268 fsp,dram-type = <1>; /* 1=DDR3L */ 269 fsp,dimm-0-enable; 270 fsp,dimm-1-enable; 271 fsp,dimm-width = <1>; /* 1=x16, 2=x32 */ 272 fsp,dimm-density = <2>; /* 2=4Gbit */ 273 fsp,dimm-bus-width = <3>; /* 3=64bits */ 274 fsp,dimm-sides = <0>; /* 0=1 ranks -> 0x2b */ 275 276 /* These following values might need a re-visit */ 277 fsp,dimm-tcl = <8>; 278 fsp,dimm-trpt-rcd = <8>; 279 fsp,dimm-twr = <8>; 280 fsp,dimm-twtr = <4>; 281 fsp,dimm-trrd = <6>; 282 fsp,dimm-trtp = <4>; 283 fsp,dimm-tfaw = <22>; 284 }; 285 }; 286 287 microcode { 288 update@0 { 289#include "microcode/m0130673325.dtsi" 290 }; 291 update@1 { 292#include "microcode/m0130679907.dtsi" 293 }; 294 }; 295}; 296