1/dts-v1/;
2
3#include <dt-bindings/gpio/x86-gpio.h>
4
5/include/ "skeleton.dtsi"
6/include/ "keyboard.dtsi"
7/include/ "serial.dtsi"
8/include/ "rtc.dtsi"
9/include/ "tsc_timer.dtsi"
10
11/ {
12	model = "Google Link";
13	compatible = "google,link", "intel,celeron-ivybridge";
14
15	aliases {
16		spi0 = &spi;
17		usb0 = &usb_0;
18		usb1 = &usb_1;
19	};
20
21	config {
22	       silent_console = <0>;
23	};
24
25	cpus {
26		#address-cells = <1>;
27		#size-cells = <0>;
28
29		cpu@0 {
30			device_type = "cpu";
31			compatible = "intel,core-gen3";
32			reg = <0>;
33			intel,apic-id = <0>;
34		};
35
36		cpu@1 {
37			device_type = "cpu";
38			compatible = "intel,core-gen3";
39			reg = <1>;
40			intel,apic-id = <1>;
41		};
42
43		cpu@2 {
44			device_type = "cpu";
45			compatible = "intel,core-gen3";
46			reg = <2>;
47			intel,apic-id = <2>;
48		};
49
50		cpu@3 {
51			device_type = "cpu";
52			compatible = "intel,core-gen3";
53			reg = <3>;
54			intel,apic-id = <3>;
55		};
56
57	};
58
59	chosen {
60		stdout-path = "/serial";
61	};
62
63	keyboard {
64		intel,duplicate-por;
65	};
66
67	pch_pinctrl {
68		compatible = "intel,x86-pinctrl";
69		u-boot,dm-pre-reloc;
70		reg = <0 0>;
71
72		gpio_a0 {
73			gpio-offset = <0 0>;
74			mode-gpio;
75			direction = <PIN_INPUT>;
76		};
77
78		gpio_a1 {
79			gpio-offset = <0>;
80			mode-gpio;
81			direction = <PIN_OUTPUT>;
82			output-value = <1>;
83		};
84
85		gpio_a3 {
86			gpio-offset = <0 3>;
87			mode-gpio;
88			direction = <PIN_INPUT>;
89		};
90
91		gpio_a5 {
92			gpio-offset = <0 5>;
93			mode-gpio;
94			direction = <PIN_INPUT>;
95		};
96
97		gpio_a6 {
98			gpio-offset = <0 6>;
99			mode-gpio;
100			direction = <PIN_OUTPUT>;
101			output-value = <1>;
102		};
103
104		gpio_a7 {
105			gpio-offset = <0 7>;
106			mode-gpio;
107			direction = <PIN_INPUT>;
108			invert;
109		};
110
111		gpio_a8 {
112			gpio-offset = <0 8>;
113			mode-gpio;
114			direction = <PIN_INPUT>;
115			invert;
116		};
117
118		gpio_a9 {
119			gpio-offset = <0 9>;
120			mode-gpio;
121			direction = <PIN_INPUT>;
122		};
123
124		gpio_a10 {
125			u-boot,dm-pre-reloc;
126			gpio-offset = <0 10>;
127			mode-gpio;
128			direction = <PIN_INPUT>;
129		};
130
131		gpio_a11 {
132			gpio-offset = <0 11>;
133			mode-gpio;
134			direction = <PIN_INPUT>;
135		};
136
137		gpio_a12 {
138			gpio-offset = <0 12>;
139			mode-gpio;
140			direction = <PIN_INPUT>;
141			invert;
142		};
143
144		gpio_a14 {
145			gpio-offset = <0 14>;
146			mode-gpio;
147			direction = <PIN_INPUT>;
148			invert;
149		};
150
151		gpio_a15 {
152			gpio-offset = <0 15>;
153			mode-gpio;
154			direction = <PIN_INPUT>;
155			invert;
156		};
157
158		gpio_a21 {
159			gpio-offset = <0 21>;
160			mode-gpio;
161			direction = <PIN_INPUT>;
162		};
163
164		gpio_a24 {
165			gpio-offset = <0 24>;
166			mode-gpio;
167			output-value = <0>;
168			direction = <PIN_OUTPUT>;
169		};
170
171		gpio_a28 {
172			gpio-offset = <0 28>;
173			mode-gpio;
174			direction = <PIN_INPUT>;
175		};
176
177		gpio_b4 {
178			gpio-offset = <0x30 4>;
179			mode-gpio;
180			direction = <PIN_OUTPUT>;
181			output-value = <1>;
182		};
183
184		gpio_b9 {
185			u-boot,dm-pre-reloc;
186			gpio-offset = <0x30 9>;
187			mode-gpio;
188			direction = <PIN_INPUT>;
189		};
190
191		gpio_b10 {
192			u-boot,dm-pre-reloc;
193			gpio-offset = <0x30 10>;
194			mode-gpio;
195			direction = <PIN_INPUT>;
196		};
197
198		gpio_b11 {
199			u-boot,dm-pre-reloc;
200			gpio-offset = <0x30 11>;
201			mode-gpio;
202			direction = <PIN_INPUT>;
203		};
204
205		gpio_b25 {
206			gpio-offset = <0x30 25>;
207			mode-gpio;
208			direction = <PIN_INPUT>;
209		};
210
211		gpio_b28 {
212			gpio-offset = <0x30 28>;
213			mode-gpio;
214			direction = <PIN_OUTPUT>;
215			output-value = <1>;
216		};
217
218	};
219
220	pci {
221		compatible = "pci-x86";
222		#address-cells = <3>;
223		#size-cells = <2>;
224		u-boot,dm-pre-reloc;
225		ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
226			0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
227			0x01000000 0x0 0x1000 0x1000 0 0xefff>;
228
229		northbridge@0,0 {
230			reg = <0x00000000 0 0 0 0>;
231			compatible = "intel,bd82x6x-northbridge";
232			board-id-gpios = <&gpio_b 9 0>, <&gpio_b 10 0>,
233					<&gpio_b 11 0>, <&gpio_a 10 0>;
234			u-boot,dm-pre-reloc;
235			spd {
236				#address-cells = <1>;
237				#size-cells = <0>;
238				elpida_4Gb_1600_x16 {
239					reg = <0>;
240					data = [92 10 0b 03 04 19 02 02
241						03 52 01 08 0a 00 fe 00
242						69 78 69 3c 69 11 18 81
243						20 08 3c 3c 01 40 83 81
244						00 00 00 00 00 00 00 00
245						00 00 00 00 00 00 00 00
246						00 00 00 00 00 00 00 00
247						00 00 00 00 0f 11 42 00
248						00 00 00 00 00 00 00 00
249						00 00 00 00 00 00 00 00
250						00 00 00 00 00 00 00 00
251						00 00 00 00 00 00 00 00
252						00 00 00 00 00 00 00 00
253						00 00 00 00 00 00 00 00
254						00 00 00 00 00 02 fe 00
255						11 52 00 00 00 07 7f 37
256						45 42 4a 32 30 55 47 36
257						45 42 55 30 2d 47 4e 2d
258						46 20 30 20 02 fe 00 00
259						00 00 00 00 00 00 00 00
260						00 00 00 00 00 00 00 00
261						00 00 00 00 00 00 00 00
262						00 00 00 00 00 00 00 00
263						00 00 00 00 00 00 00 00
264						00 00 00 00 00 00 00 00
265						00 00 00 00 00 00 00 00
266						00 00 00 00 00 00 00 00
267						00 00 00 00 00 00 00 00
268						00 00 00 00 00 00 00 00
269						00 00 00 00 00 00 00 00
270						00 00 00 00 00 00 00 00
271						00 00 00 00 00 00 00 00];
272				};
273				samsung_4Gb_1600_1.35v_x16 {
274					reg = <1>;
275					data = [92 11 0b 03 04 19 02 02
276						03 11 01 08 0a 00 fe 00
277						69 78 69 3c 69 11 18 81
278						f0 0a 3c 3c 01 40 83 01
279						00 80 00 00 00 00 00 00
280						00 00 00 00 00 00 00 00
281						00 00 00 00 00 00 00 00
282						00 00 00 00 0f 11 02 00
283						00 00 00 00 00 00 00 00
284						00 00 00 00 00 00 00 00
285						00 00 00 00 00 00 00 00
286						00 00 00 00 00 00 00 00
287						00 00 00 00 00 00 00 00
288						00 00 00 00 00 00 00 00
289						00 00 00 00 00 80 ce 01
290						00 00 00 00 00 00 6a 04
291						4d 34 37 31 42 35 36 37
292						34 42 48 30 2d 59 4b 30
293						20 20 00 00 80 ce 00 00
294						00 00 00 00 00 00 00 00
295						00 00 00 00 00 00 00 00
296						00 00 00 00 00 00 00 00
297						00 00 00 00 00 00 00 00
298						00 00 00 00 00 00 00 00
299						00 00 00 00 00 00 00 00
300						00 00 00 00 00 00 00 00
301						00 00 00 00 00 00 00 00
302						00 00 00 00 00 00 00 00
303						00 00 00 00 00 00 00 00
304						00 00 00 00 00 00 00 00
305						00 00 00 00 00 00 00 00
306						00 00 00 00 00 00 00 00];
307					};
308				micron_4Gb_1600_1.35v_x16 {
309					reg = <2>;
310					data = [92 11 0b 03 04 19 02 02
311						03 11 01 08 0a 00 fe 00
312						69 78 69 3c 69 11 18 81
313						20 08 3c 3c 01 40 83 05
314						00 00 00 00 00 00 00 00
315						00 00 00 00 00 00 00 00
316						00 00 00 00 00 00 00 00
317						00 00 00 00 0f 01 02 00
318						00 00 00 00 00 00 00 00
319						00 00 00 00 00 00 00 00
320						00 00 00 00 00 00 00 00
321						00 00 00 00 00 00 00 00
322						00 00 00 00 00 00 00 00
323						00 00 00 00 00 00 00 00
324						00 00 00 00 00 80 2c 00
325						00 00 00 00 00 00 ad 75
326						34 4b 54 46 32 35 36 36
327						34 48 5a 2d 31 47 36 45
328						31 20 45 31 80 2c 00 00
329						00 00 00 00 00 00 00 00
330						00 00 00 00 00 00 00 00
331						00 00 00 00 00 00 00 00
332						ff ff ff ff ff ff ff ff
333						ff ff ff ff ff ff ff ff
334						ff ff ff ff ff ff ff ff
335						ff ff ff ff ff ff ff ff
336						ff ff ff ff ff ff ff ff
337						ff ff ff ff ff ff ff ff
338						ff ff ff ff ff ff ff ff
339						ff ff ff ff ff ff ff ff
340						ff ff ff ff ff ff ff ff
341						ff ff ff ff ff ff ff ff];
342				};
343			};
344		};
345
346		gma@2,0 {
347			reg = <0x00001000 0 0 0 0>;
348			compatible = "intel,gma";
349			intel,dp_hotplug = <0 0 0x06>;
350			intel,panel-port-select = <1>;
351			intel,panel-power-cycle-delay = <6>;
352			intel,panel-power-up-delay = <2000>;
353			intel,panel-power-down-delay = <500>;
354			intel,panel-power-backlight-on-delay = <2000>;
355			intel,panel-power-backlight-off-delay = <2000>;
356			intel,cpu-backlight = <0x00000200>;
357			intel,pch-backlight = <0x04000000>;
358		};
359
360		me@16,0 {
361			reg = <0x0000b000 0 0 0 0>;
362			compatible = "intel,me";
363			u-boot,dm-pre-reloc;
364		};
365
366		usb_1: usb@1a,0 {
367			reg = <0x0000d000 0 0 0 0>;
368			compatible = "ehci-pci";
369		};
370
371		usb_0: usb@1d,0 {
372			reg = <0x0000e800 0 0 0 0>;
373			compatible = "ehci-pci";
374		};
375
376		pch@1f,0 {
377			reg = <0x0000f800 0 0 0 0>;
378			compatible = "intel,bd82x6x", "intel,pch9";
379			u-boot,dm-pre-reloc;
380			#address-cells = <1>;
381			#size-cells = <1>;
382			intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
383						0x80 0x80 0x80 0x80>;
384			intel,gpi-routing = <0 0 0 0 0 0 0 2
385						1 0 0 0 0 0 0 0>;
386			/* Enable EC SMI source */
387			intel,alt-gp-smi-enable = <0x0100>;
388
389			spi: spi {
390				#address-cells = <1>;
391				#size-cells = <0>;
392				compatible = "intel,ich9-spi";
393				spi-flash@0 {
394					#size-cells = <1>;
395					#address-cells = <1>;
396					reg = <0>;
397					compatible = "winbond,w25q64",
398							"spi-flash";
399					memory-map = <0xff800000 0x00800000>;
400					rw-mrc-cache {
401						label = "rw-mrc-cache";
402						reg = <0x003e0000 0x00010000>;
403					};
404				};
405			};
406
407			gpio_a: gpioa {
408				compatible = "intel,ich6-gpio";
409				u-boot,dm-pre-reloc;
410				#gpio-cells = <2>;
411				gpio-controller;
412				reg = <0 0x10>;
413				bank-name = "A";
414			};
415
416			gpio_b: gpiob {
417				compatible = "intel,ich6-gpio";
418				u-boot,dm-pre-reloc;
419				#gpio-cells = <2>;
420				gpio-controller;
421				reg = <0x30 0x10>;
422				bank-name = "B";
423			};
424
425			gpio_c: gpioc {
426				compatible = "intel,ich6-gpio";
427				u-boot,dm-pre-reloc;
428				#gpio-cells = <2>;
429				gpio-controller;
430				reg = <0x40 0x10>;
431				bank-name = "C";
432			};
433
434			lpc {
435				compatible = "intel,bd82x6x-lpc";
436				#address-cells = <1>;
437				#size-cells = <0>;
438				u-boot,dm-pre-reloc;
439				intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
440				cros-ec@200 {
441					compatible = "google,cros-ec";
442					reg = <0x204 1 0x200 1 0x880 0x80>;
443
444					/*
445					 * Describes the flash memory within
446					 * the EC
447					 */
448					#address-cells = <1>;
449					#size-cells = <1>;
450					flash@8000000 {
451						reg = <0x08000000 0x20000>;
452						erase-value = <0xff>;
453					};
454				};
455			};
456		};
457
458		sata@1f,2 {
459			compatible = "intel,pantherpoint-ahci";
460			reg = <0x0000fa00 0 0 0 0>;
461			u-boot,dm-pre-reloc;
462			intel,sata-mode = "ahci";
463			intel,sata-port-map = <1>;
464			intel,sata-port0-gen3-tx = <0x00880a7f>;
465		};
466
467		smbus: smbus@1f,3 {
468			compatible = "intel,ich-i2c";
469			reg = <0x0000fb00 0 0 0 0>;
470			u-boot,dm-pre-reloc;
471		};
472	};
473
474	tpm {
475		reg = <0xfed40000 0x5000>;
476		compatible = "infineon,slb9635lpc";
477	};
478
479	microcode {
480		update@0 {
481#include "microcode/m12306a9_0000001b.dtsi"
482		};
483	};
484
485};
486