1/dts-v1/;
2
3#include <dt-bindings/gpio/x86-gpio.h>
4
5/include/ "skeleton.dtsi"
6/include/ "keyboard.dtsi"
7/include/ "serial.dtsi"
8/include/ "rtc.dtsi"
9/include/ "tsc_timer.dtsi"
10/include/ "coreboot_fb.dtsi"
11
12/ {
13	model = "Google Link";
14	compatible = "google,link", "intel,celeron-ivybridge";
15
16	aliases {
17		spi0 = &spi;
18		usb0 = &usb_0;
19		usb1 = &usb_1;
20	};
21
22	config {
23	       silent_console = <0>;
24	};
25
26	cpus {
27		#address-cells = <1>;
28		#size-cells = <0>;
29
30		cpu@0 {
31			device_type = "cpu";
32			compatible = "intel,core-gen3";
33			reg = <0>;
34			intel,apic-id = <0>;
35		};
36
37		cpu@1 {
38			device_type = "cpu";
39			compatible = "intel,core-gen3";
40			reg = <1>;
41			intel,apic-id = <1>;
42		};
43
44		cpu@2 {
45			device_type = "cpu";
46			compatible = "intel,core-gen3";
47			reg = <2>;
48			intel,apic-id = <2>;
49		};
50
51		cpu@3 {
52			device_type = "cpu";
53			compatible = "intel,core-gen3";
54			reg = <3>;
55			intel,apic-id = <3>;
56		};
57
58	};
59
60	chosen {
61		stdout-path = "/serial";
62	};
63
64	keyboard {
65		intel,duplicate-por;
66	};
67
68	pch_pinctrl {
69		compatible = "intel,x86-pinctrl";
70		u-boot,dm-pre-reloc;
71		reg = <0 0>;
72
73		gpio_a0 {
74			gpio-offset = <0 0>;
75			mode-gpio;
76			direction = <PIN_INPUT>;
77		};
78
79		gpio_a1 {
80			gpio-offset = <0>;
81			mode-gpio;
82			direction = <PIN_OUTPUT>;
83			output-value = <1>;
84		};
85
86		gpio_a3 {
87			gpio-offset = <0 3>;
88			mode-gpio;
89			direction = <PIN_INPUT>;
90		};
91
92		gpio_a5 {
93			gpio-offset = <0 5>;
94			mode-gpio;
95			direction = <PIN_INPUT>;
96		};
97
98		gpio_a6 {
99			gpio-offset = <0 6>;
100			mode-gpio;
101			direction = <PIN_OUTPUT>;
102			output-value = <1>;
103		};
104
105		gpio_a7 {
106			gpio-offset = <0 7>;
107			mode-gpio;
108			direction = <PIN_INPUT>;
109			invert;
110		};
111
112		gpio_a8 {
113			gpio-offset = <0 8>;
114			mode-gpio;
115			direction = <PIN_INPUT>;
116			invert;
117		};
118
119		gpio_a9 {
120			gpio-offset = <0 9>;
121			mode-gpio;
122			direction = <PIN_INPUT>;
123		};
124
125		gpio_a10 {
126			u-boot,dm-pre-reloc;
127			gpio-offset = <0 10>;
128			mode-gpio;
129			direction = <PIN_INPUT>;
130		};
131
132		gpio_a11 {
133			gpio-offset = <0 11>;
134			mode-gpio;
135			direction = <PIN_INPUT>;
136		};
137
138		gpio_a12 {
139			gpio-offset = <0 12>;
140			mode-gpio;
141			direction = <PIN_INPUT>;
142			invert;
143		};
144
145		gpio_a14 {
146			gpio-offset = <0 14>;
147			mode-gpio;
148			direction = <PIN_INPUT>;
149			invert;
150		};
151
152		gpio_a15 {
153			gpio-offset = <0 15>;
154			mode-gpio;
155			direction = <PIN_INPUT>;
156			invert;
157		};
158
159		gpio_a21 {
160			gpio-offset = <0 21>;
161			mode-gpio;
162			direction = <PIN_INPUT>;
163		};
164
165		gpio_a24 {
166			gpio-offset = <0 24>;
167			mode-gpio;
168			output-value = <0>;
169			direction = <PIN_OUTPUT>;
170		};
171
172		gpio_a28 {
173			gpio-offset = <0 28>;
174			mode-gpio;
175			direction = <PIN_INPUT>;
176		};
177
178		gpio_b4 {
179			gpio-offset = <0x30 4>;
180			mode-gpio;
181			direction = <PIN_OUTPUT>;
182			output-value = <1>;
183		};
184
185		gpio_b9 {
186			u-boot,dm-pre-reloc;
187			gpio-offset = <0x30 9>;
188			mode-gpio;
189			direction = <PIN_INPUT>;
190		};
191
192		gpio_b10 {
193			u-boot,dm-pre-reloc;
194			gpio-offset = <0x30 10>;
195			mode-gpio;
196			direction = <PIN_INPUT>;
197		};
198
199		gpio_b11 {
200			u-boot,dm-pre-reloc;
201			gpio-offset = <0x30 11>;
202			mode-gpio;
203			direction = <PIN_INPUT>;
204		};
205
206		gpio_b25 {
207			gpio-offset = <0x30 25>;
208			mode-gpio;
209			direction = <PIN_INPUT>;
210		};
211
212		gpio_b28 {
213			gpio-offset = <0x30 28>;
214			mode-gpio;
215			direction = <PIN_OUTPUT>;
216			output-value = <1>;
217		};
218
219	};
220
221	pci {
222		compatible = "pci-x86";
223		#address-cells = <3>;
224		#size-cells = <2>;
225		u-boot,dm-pre-reloc;
226		ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
227			0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
228			0x01000000 0x0 0x1000 0x1000 0 0xefff>;
229
230		northbridge@0,0 {
231			reg = <0x00000000 0 0 0 0>;
232			u-boot,dm-pre-reloc;
233			compatible = "intel,bd82x6x-northbridge";
234			board-id-gpios = <&gpio_b 9 0>, <&gpio_b 10 0>,
235					<&gpio_b 11 0>, <&gpio_a 10 0>;
236			spd {
237				u-boot,dm-pre-reloc;
238				#address-cells = <1>;
239				#size-cells = <0>;
240				elpida_4Gb_1600_x16 {
241					u-boot,dm-pre-reloc;
242					reg = <0>;
243					data = [92 10 0b 03 04 19 02 02
244						03 52 01 08 0a 00 fe 00
245						69 78 69 3c 69 11 18 81
246						20 08 3c 3c 01 40 83 81
247						00 00 00 00 00 00 00 00
248						00 00 00 00 00 00 00 00
249						00 00 00 00 00 00 00 00
250						00 00 00 00 0f 11 42 00
251						00 00 00 00 00 00 00 00
252						00 00 00 00 00 00 00 00
253						00 00 00 00 00 00 00 00
254						00 00 00 00 00 00 00 00
255						00 00 00 00 00 00 00 00
256						00 00 00 00 00 00 00 00
257						00 00 00 00 00 02 fe 00
258						11 52 00 00 00 07 7f 37
259						45 42 4a 32 30 55 47 36
260						45 42 55 30 2d 47 4e 2d
261						46 20 30 20 02 fe 00 00
262						00 00 00 00 00 00 00 00
263						00 00 00 00 00 00 00 00
264						00 00 00 00 00 00 00 00
265						00 00 00 00 00 00 00 00
266						00 00 00 00 00 00 00 00
267						00 00 00 00 00 00 00 00
268						00 00 00 00 00 00 00 00
269						00 00 00 00 00 00 00 00
270						00 00 00 00 00 00 00 00
271						00 00 00 00 00 00 00 00
272						00 00 00 00 00 00 00 00
273						00 00 00 00 00 00 00 00
274						00 00 00 00 00 00 00 00];
275				};
276				samsung_4Gb_1600_1.35v_x16 {
277					u-boot,dm-pre-reloc;
278					reg = <1>;
279					data = [92 11 0b 03 04 19 02 02
280						03 11 01 08 0a 00 fe 00
281						69 78 69 3c 69 11 18 81
282						f0 0a 3c 3c 01 40 83 01
283						00 80 00 00 00 00 00 00
284						00 00 00 00 00 00 00 00
285						00 00 00 00 00 00 00 00
286						00 00 00 00 0f 11 02 00
287						00 00 00 00 00 00 00 00
288						00 00 00 00 00 00 00 00
289						00 00 00 00 00 00 00 00
290						00 00 00 00 00 00 00 00
291						00 00 00 00 00 00 00 00
292						00 00 00 00 00 00 00 00
293						00 00 00 00 00 80 ce 01
294						00 00 00 00 00 00 6a 04
295						4d 34 37 31 42 35 36 37
296						34 42 48 30 2d 59 4b 30
297						20 20 00 00 80 ce 00 00
298						00 00 00 00 00 00 00 00
299						00 00 00 00 00 00 00 00
300						00 00 00 00 00 00 00 00
301						00 00 00 00 00 00 00 00
302						00 00 00 00 00 00 00 00
303						00 00 00 00 00 00 00 00
304						00 00 00 00 00 00 00 00
305						00 00 00 00 00 00 00 00
306						00 00 00 00 00 00 00 00
307						00 00 00 00 00 00 00 00
308						00 00 00 00 00 00 00 00
309						00 00 00 00 00 00 00 00
310						00 00 00 00 00 00 00 00];
311					};
312				micron_4Gb_1600_1.35v_x16 {
313					reg = <2>;
314					data = [92 11 0b 03 04 19 02 02
315						03 11 01 08 0a 00 fe 00
316						69 78 69 3c 69 11 18 81
317						20 08 3c 3c 01 40 83 05
318						00 00 00 00 00 00 00 00
319						00 00 00 00 00 00 00 00
320						00 00 00 00 00 00 00 00
321						00 00 00 00 0f 01 02 00
322						00 00 00 00 00 00 00 00
323						00 00 00 00 00 00 00 00
324						00 00 00 00 00 00 00 00
325						00 00 00 00 00 00 00 00
326						00 00 00 00 00 00 00 00
327						00 00 00 00 00 00 00 00
328						00 00 00 00 00 80 2c 00
329						00 00 00 00 00 00 ad 75
330						34 4b 54 46 32 35 36 36
331						34 48 5a 2d 31 47 36 45
332						31 20 45 31 80 2c 00 00
333						00 00 00 00 00 00 00 00
334						00 00 00 00 00 00 00 00
335						00 00 00 00 00 00 00 00
336						ff ff ff ff ff ff ff ff
337						ff ff ff ff ff ff ff ff
338						ff ff ff ff ff ff ff ff
339						ff ff ff ff ff ff ff ff
340						ff ff ff ff ff ff ff ff
341						ff ff ff ff ff ff ff ff
342						ff ff ff ff ff ff ff ff
343						ff ff ff ff ff ff ff ff
344						ff ff ff ff ff ff ff ff
345						ff ff ff ff ff ff ff ff];
346				};
347			};
348		};
349
350		gma@2,0 {
351			reg = <0x00001000 0 0 0 0>;
352			compatible = "intel,gma";
353			intel,dp_hotplug = <0 0 0x06>;
354			intel,panel-port-select = <1>;
355			intel,panel-power-cycle-delay = <6>;
356			intel,panel-power-up-delay = <2000>;
357			intel,panel-power-down-delay = <500>;
358			intel,panel-power-backlight-on-delay = <2000>;
359			intel,panel-power-backlight-off-delay = <2000>;
360			intel,cpu-backlight = <0x00000200>;
361			intel,pch-backlight = <0x04000000>;
362		};
363
364		me@16,0 {
365			reg = <0x0000b000 0 0 0 0>;
366			compatible = "intel,me";
367			u-boot,dm-pre-reloc;
368		};
369
370		usb_1: usb@1a,0 {
371			reg = <0x0000d000 0 0 0 0>;
372			compatible = "ehci-pci";
373		};
374
375		usb_0: usb@1d,0 {
376			reg = <0x0000e800 0 0 0 0>;
377			compatible = "ehci-pci";
378		};
379
380		pch@1f,0 {
381			reg = <0x0000f800 0 0 0 0>;
382			compatible = "intel,bd82x6x", "intel,pch9";
383			u-boot,dm-pre-reloc;
384			#address-cells = <1>;
385			#size-cells = <1>;
386			intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
387						0x80 0x80 0x80 0x80>;
388			intel,gpi-routing = <0 0 0 0 0 0 0 2
389						1 0 0 0 0 0 0 0>;
390			/* Enable EC SMI source */
391			intel,alt-gp-smi-enable = <0x0100>;
392
393			spi: spi {
394				#address-cells = <1>;
395				#size-cells = <0>;
396				compatible = "intel,ich9-spi";
397				u-boot,dm-pre-reloc;
398				spi-flash@0 {
399					#size-cells = <1>;
400					#address-cells = <1>;
401					u-boot,dm-pre-reloc;
402					reg = <0>;
403					compatible = "winbond,w25q64",
404							"spi-flash";
405					memory-map = <0xff800000 0x00800000>;
406					rw-mrc-cache {
407						label = "rw-mrc-cache";
408						reg = <0x003e0000 0x00010000>;
409						u-boot,dm-pre-reloc;
410					};
411				};
412			};
413
414			gpio_a: gpioa {
415				compatible = "intel,ich6-gpio";
416				u-boot,dm-pre-reloc;
417				#gpio-cells = <2>;
418				gpio-controller;
419				reg = <0 0x10>;
420				bank-name = "A";
421			};
422
423			gpio_b: gpiob {
424				compatible = "intel,ich6-gpio";
425				u-boot,dm-pre-reloc;
426				#gpio-cells = <2>;
427				gpio-controller;
428				reg = <0x30 0x10>;
429				bank-name = "B";
430			};
431
432			gpio_c: gpioc {
433				compatible = "intel,ich6-gpio";
434				u-boot,dm-pre-reloc;
435				#gpio-cells = <2>;
436				gpio-controller;
437				reg = <0x40 0x10>;
438				bank-name = "C";
439			};
440
441			lpc {
442				compatible = "intel,bd82x6x-lpc";
443				#address-cells = <1>;
444				#size-cells = <0>;
445				u-boot,dm-pre-reloc;
446				intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
447				cros-ec@200 {
448					compatible = "google,cros-ec";
449					reg = <0x204 1 0x200 1 0x880 0x80>;
450
451					/*
452					 * Describes the flash memory within
453					 * the EC
454					 */
455					#address-cells = <1>;
456					#size-cells = <1>;
457					flash@8000000 {
458						reg = <0x08000000 0x20000>;
459						erase-value = <0xff>;
460					};
461				};
462			};
463		};
464
465		sata@1f,2 {
466			compatible = "intel,pantherpoint-ahci";
467			reg = <0x0000fa00 0 0 0 0>;
468			u-boot,dm-pre-reloc;
469			intel,sata-mode = "ahci";
470			intel,sata-port-map = <1>;
471			intel,sata-port0-gen3-tx = <0x00880a7f>;
472		};
473
474		smbus: smbus@1f,3 {
475			compatible = "intel,ich-i2c";
476			reg = <0x0000fb00 0 0 0 0>;
477			u-boot,dm-pre-reloc;
478		};
479	};
480
481	tpm {
482		reg = <0xfed40000 0x5000>;
483		compatible = "infineon,slb9635lpc";
484	};
485
486	microcode {
487		u-boot,dm-pre-reloc;
488		update@0 {
489			u-boot,dm-pre-reloc;
490#include "microcode/m12306a9_0000001b.dtsi"
491		};
492	};
493
494};
495