1/dts-v1/;
2
3#include <dt-bindings/gpio/x86-gpio.h>
4
5/include/ "skeleton.dtsi"
6/include/ "keyboard.dtsi"
7/include/ "serial.dtsi"
8/include/ "reset.dtsi"
9/include/ "rtc.dtsi"
10/include/ "tsc_timer.dtsi"
11/include/ "coreboot_fb.dtsi"
12
13/ {
14	model = "Google Link";
15	compatible = "google,link", "intel,celeron-ivybridge";
16
17	aliases {
18		spi0 = &spi;
19		usb0 = &usb_0;
20		usb1 = &usb_1;
21	};
22
23	config {
24	       silent_console = <0>;
25	};
26
27	cpus {
28		#address-cells = <1>;
29		#size-cells = <0>;
30
31		cpu@0 {
32			device_type = "cpu";
33			compatible = "intel,core-gen3";
34			reg = <0>;
35			intel,apic-id = <0>;
36		};
37
38		cpu@1 {
39			device_type = "cpu";
40			compatible = "intel,core-gen3";
41			reg = <1>;
42			intel,apic-id = <1>;
43		};
44
45		cpu@2 {
46			device_type = "cpu";
47			compatible = "intel,core-gen3";
48			reg = <2>;
49			intel,apic-id = <2>;
50		};
51
52		cpu@3 {
53			device_type = "cpu";
54			compatible = "intel,core-gen3";
55			reg = <3>;
56			intel,apic-id = <3>;
57		};
58
59	};
60
61	chosen {
62		stdout-path = "/serial";
63	};
64
65	keyboard {
66		intel,duplicate-por;
67	};
68
69	pch_pinctrl {
70		compatible = "intel,x86-pinctrl";
71		u-boot,dm-pre-reloc;
72		reg = <0 0>;
73
74		gpio_a0 {
75			gpio-offset = <0 0>;
76			mode-gpio;
77			direction = <PIN_INPUT>;
78		};
79
80		gpio_a1 {
81			gpio-offset = <0>;
82			mode-gpio;
83			direction = <PIN_OUTPUT>;
84			output-value = <1>;
85		};
86
87		gpio_a3 {
88			gpio-offset = <0 3>;
89			mode-gpio;
90			direction = <PIN_INPUT>;
91		};
92
93		gpio_a5 {
94			gpio-offset = <0 5>;
95			mode-gpio;
96			direction = <PIN_INPUT>;
97		};
98
99		gpio_a6 {
100			gpio-offset = <0 6>;
101			mode-gpio;
102			direction = <PIN_OUTPUT>;
103			output-value = <1>;
104		};
105
106		gpio_a7 {
107			gpio-offset = <0 7>;
108			mode-gpio;
109			direction = <PIN_INPUT>;
110			invert;
111		};
112
113		gpio_a8 {
114			gpio-offset = <0 8>;
115			mode-gpio;
116			direction = <PIN_INPUT>;
117			invert;
118		};
119
120		gpio_a9 {
121			gpio-offset = <0 9>;
122			mode-gpio;
123			direction = <PIN_INPUT>;
124		};
125
126		gpio_a10 {
127			u-boot,dm-pre-reloc;
128			gpio-offset = <0 10>;
129			mode-gpio;
130			direction = <PIN_INPUT>;
131		};
132
133		gpio_a11 {
134			gpio-offset = <0 11>;
135			mode-gpio;
136			direction = <PIN_INPUT>;
137		};
138
139		gpio_a12 {
140			gpio-offset = <0 12>;
141			mode-gpio;
142			direction = <PIN_INPUT>;
143			invert;
144		};
145
146		gpio_a14 {
147			gpio-offset = <0 14>;
148			mode-gpio;
149			direction = <PIN_INPUT>;
150			invert;
151		};
152
153		gpio_a15 {
154			gpio-offset = <0 15>;
155			mode-gpio;
156			direction = <PIN_INPUT>;
157			invert;
158		};
159
160		gpio_a21 {
161			gpio-offset = <0 21>;
162			mode-gpio;
163			direction = <PIN_INPUT>;
164		};
165
166		gpio_a24 {
167			gpio-offset = <0 24>;
168			mode-gpio;
169			output-value = <0>;
170			direction = <PIN_OUTPUT>;
171		};
172
173		gpio_a28 {
174			gpio-offset = <0 28>;
175			mode-gpio;
176			direction = <PIN_INPUT>;
177		};
178
179		gpio_b4 {
180			gpio-offset = <0x30 4>;
181			mode-gpio;
182			direction = <PIN_OUTPUT>;
183			output-value = <1>;
184		};
185
186		gpio_b9 {
187			u-boot,dm-pre-reloc;
188			gpio-offset = <0x30 9>;
189			mode-gpio;
190			direction = <PIN_INPUT>;
191		};
192
193		gpio_b10 {
194			u-boot,dm-pre-reloc;
195			gpio-offset = <0x30 10>;
196			mode-gpio;
197			direction = <PIN_INPUT>;
198		};
199
200		gpio_b11 {
201			u-boot,dm-pre-reloc;
202			gpio-offset = <0x30 11>;
203			mode-gpio;
204			direction = <PIN_INPUT>;
205		};
206
207		gpio_b25 {
208			gpio-offset = <0x30 25>;
209			mode-gpio;
210			direction = <PIN_INPUT>;
211		};
212
213		gpio_b28 {
214			gpio-offset = <0x30 28>;
215			mode-gpio;
216			direction = <PIN_OUTPUT>;
217			output-value = <1>;
218		};
219
220	};
221
222	pci {
223		compatible = "pci-x86";
224		#address-cells = <3>;
225		#size-cells = <2>;
226		u-boot,dm-pre-reloc;
227		ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
228			0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
229			0x01000000 0x0 0x1000 0x1000 0 0xefff>;
230
231		northbridge@0,0 {
232			reg = <0x00000000 0 0 0 0>;
233			u-boot,dm-pre-reloc;
234			compatible = "intel,bd82x6x-northbridge";
235			board-id-gpios = <&gpio_b 9 0>, <&gpio_b 10 0>,
236					<&gpio_b 11 0>, <&gpio_a 10 0>;
237			spd {
238				u-boot,dm-pre-reloc;
239				#address-cells = <1>;
240				#size-cells = <0>;
241				elpida_4Gb_1600_x16 {
242					u-boot,dm-pre-reloc;
243					reg = <0>;
244					data = [92 10 0b 03 04 19 02 02
245						03 52 01 08 0a 00 fe 00
246						69 78 69 3c 69 11 18 81
247						20 08 3c 3c 01 40 83 81
248						00 00 00 00 00 00 00 00
249						00 00 00 00 00 00 00 00
250						00 00 00 00 00 00 00 00
251						00 00 00 00 0f 11 42 00
252						00 00 00 00 00 00 00 00
253						00 00 00 00 00 00 00 00
254						00 00 00 00 00 00 00 00
255						00 00 00 00 00 00 00 00
256						00 00 00 00 00 00 00 00
257						00 00 00 00 00 00 00 00
258						00 00 00 00 00 02 fe 00
259						11 52 00 00 00 07 7f 37
260						45 42 4a 32 30 55 47 36
261						45 42 55 30 2d 47 4e 2d
262						46 20 30 20 02 fe 00 00
263						00 00 00 00 00 00 00 00
264						00 00 00 00 00 00 00 00
265						00 00 00 00 00 00 00 00
266						00 00 00 00 00 00 00 00
267						00 00 00 00 00 00 00 00
268						00 00 00 00 00 00 00 00
269						00 00 00 00 00 00 00 00
270						00 00 00 00 00 00 00 00
271						00 00 00 00 00 00 00 00
272						00 00 00 00 00 00 00 00
273						00 00 00 00 00 00 00 00
274						00 00 00 00 00 00 00 00
275						00 00 00 00 00 00 00 00];
276				};
277				samsung_4Gb_1600_1.35v_x16 {
278					u-boot,dm-pre-reloc;
279					reg = <1>;
280					data = [92 11 0b 03 04 19 02 02
281						03 11 01 08 0a 00 fe 00
282						69 78 69 3c 69 11 18 81
283						f0 0a 3c 3c 01 40 83 01
284						00 80 00 00 00 00 00 00
285						00 00 00 00 00 00 00 00
286						00 00 00 00 00 00 00 00
287						00 00 00 00 0f 11 02 00
288						00 00 00 00 00 00 00 00
289						00 00 00 00 00 00 00 00
290						00 00 00 00 00 00 00 00
291						00 00 00 00 00 00 00 00
292						00 00 00 00 00 00 00 00
293						00 00 00 00 00 00 00 00
294						00 00 00 00 00 80 ce 01
295						00 00 00 00 00 00 6a 04
296						4d 34 37 31 42 35 36 37
297						34 42 48 30 2d 59 4b 30
298						20 20 00 00 80 ce 00 00
299						00 00 00 00 00 00 00 00
300						00 00 00 00 00 00 00 00
301						00 00 00 00 00 00 00 00
302						00 00 00 00 00 00 00 00
303						00 00 00 00 00 00 00 00
304						00 00 00 00 00 00 00 00
305						00 00 00 00 00 00 00 00
306						00 00 00 00 00 00 00 00
307						00 00 00 00 00 00 00 00
308						00 00 00 00 00 00 00 00
309						00 00 00 00 00 00 00 00
310						00 00 00 00 00 00 00 00
311						00 00 00 00 00 00 00 00];
312					};
313				micron_4Gb_1600_1.35v_x16 {
314					reg = <2>;
315					data = [92 11 0b 03 04 19 02 02
316						03 11 01 08 0a 00 fe 00
317						69 78 69 3c 69 11 18 81
318						20 08 3c 3c 01 40 83 05
319						00 00 00 00 00 00 00 00
320						00 00 00 00 00 00 00 00
321						00 00 00 00 00 00 00 00
322						00 00 00 00 0f 01 02 00
323						00 00 00 00 00 00 00 00
324						00 00 00 00 00 00 00 00
325						00 00 00 00 00 00 00 00
326						00 00 00 00 00 00 00 00
327						00 00 00 00 00 00 00 00
328						00 00 00 00 00 00 00 00
329						00 00 00 00 00 80 2c 00
330						00 00 00 00 00 00 ad 75
331						34 4b 54 46 32 35 36 36
332						34 48 5a 2d 31 47 36 45
333						31 20 45 31 80 2c 00 00
334						00 00 00 00 00 00 00 00
335						00 00 00 00 00 00 00 00
336						00 00 00 00 00 00 00 00
337						ff ff ff ff ff ff ff ff
338						ff ff ff ff ff ff ff ff
339						ff ff ff ff ff ff ff ff
340						ff ff ff ff ff ff ff ff
341						ff ff ff ff ff ff ff ff
342						ff ff ff ff ff ff ff ff
343						ff ff ff ff ff ff ff ff
344						ff ff ff ff ff ff ff ff
345						ff ff ff ff ff ff ff ff
346						ff ff ff ff ff ff ff ff];
347				};
348			};
349		};
350
351		gma@2,0 {
352			reg = <0x00001000 0 0 0 0>;
353			compatible = "intel,gma";
354			intel,dp_hotplug = <0 0 0x06>;
355			intel,panel-port-select = <1>;
356			intel,panel-power-cycle-delay = <6>;
357			intel,panel-power-up-delay = <2000>;
358			intel,panel-power-down-delay = <500>;
359			intel,panel-power-backlight-on-delay = <2000>;
360			intel,panel-power-backlight-off-delay = <2000>;
361			intel,cpu-backlight = <0x00000200>;
362			intel,pch-backlight = <0x04000000>;
363		};
364
365		me@16,0 {
366			reg = <0x0000b000 0 0 0 0>;
367			compatible = "intel,me";
368			u-boot,dm-pre-reloc;
369		};
370
371		usb_1: usb@1a,0 {
372			reg = <0x0000d000 0 0 0 0>;
373			compatible = "ehci-pci";
374		};
375
376		usb_0: usb@1d,0 {
377			reg = <0x0000e800 0 0 0 0>;
378			compatible = "ehci-pci";
379		};
380
381		pch@1f,0 {
382			reg = <0x0000f800 0 0 0 0>;
383			compatible = "intel,bd82x6x", "intel,pch9";
384			u-boot,dm-pre-reloc;
385			#address-cells = <1>;
386			#size-cells = <1>;
387			intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
388						0x80 0x80 0x80 0x80>;
389			intel,gpi-routing = <0 0 0 0 0 0 0 2
390						1 0 0 0 0 0 0 0>;
391			/* Enable EC SMI source */
392			intel,alt-gp-smi-enable = <0x0100>;
393
394			spi: spi {
395				#address-cells = <1>;
396				#size-cells = <0>;
397				compatible = "intel,ich9-spi";
398				u-boot,dm-pre-reloc;
399				spi-flash@0 {
400					#size-cells = <1>;
401					#address-cells = <1>;
402					u-boot,dm-pre-reloc;
403					reg = <0>;
404					compatible = "winbond,w25q64",
405							"spi-flash";
406					memory-map = <0xff800000 0x00800000>;
407					rw-mrc-cache {
408						label = "rw-mrc-cache";
409						reg = <0x003e0000 0x00010000>;
410						u-boot,dm-pre-reloc;
411					};
412				};
413			};
414
415			gpio_a: gpioa {
416				compatible = "intel,ich6-gpio";
417				u-boot,dm-pre-reloc;
418				#gpio-cells = <2>;
419				gpio-controller;
420				reg = <0 0x10>;
421				bank-name = "A";
422			};
423
424			gpio_b: gpiob {
425				compatible = "intel,ich6-gpio";
426				u-boot,dm-pre-reloc;
427				#gpio-cells = <2>;
428				gpio-controller;
429				reg = <0x30 0x10>;
430				bank-name = "B";
431			};
432
433			gpio_c: gpioc {
434				compatible = "intel,ich6-gpio";
435				u-boot,dm-pre-reloc;
436				#gpio-cells = <2>;
437				gpio-controller;
438				reg = <0x40 0x10>;
439				bank-name = "C";
440			};
441
442			lpc {
443				compatible = "intel,bd82x6x-lpc";
444				#address-cells = <1>;
445				#size-cells = <0>;
446				u-boot,dm-pre-reloc;
447				intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
448				cros-ec@200 {
449					compatible = "google,cros-ec";
450					reg = <0x204 1 0x200 1 0x880 0x80>;
451
452					/*
453					 * Describes the flash memory within
454					 * the EC
455					 */
456					#address-cells = <1>;
457					#size-cells = <1>;
458					flash@8000000 {
459						reg = <0x08000000 0x20000>;
460						erase-value = <0xff>;
461					};
462				};
463			};
464		};
465
466		sata@1f,2 {
467			compatible = "intel,pantherpoint-ahci";
468			reg = <0x0000fa00 0 0 0 0>;
469			u-boot,dm-pre-reloc;
470			intel,sata-mode = "ahci";
471			intel,sata-port-map = <1>;
472			intel,sata-port0-gen3-tx = <0x00880a7f>;
473		};
474
475		smbus: smbus@1f,3 {
476			compatible = "intel,ich-i2c";
477			reg = <0x0000fb00 0 0 0 0>;
478			u-boot,dm-pre-reloc;
479		};
480	};
481
482	tpm {
483		reg = <0xfed40000 0x5000>;
484		compatible = "infineon,slb9635lpc";
485	};
486
487	microcode {
488		u-boot,dm-pre-reloc;
489		update@0 {
490			u-boot,dm-pre-reloc;
491#include "microcode/m12306a9_0000001b.dtsi"
492		};
493	};
494
495};
496