1*ade8127aSBin Meng/dts-v1/; 2*ade8127aSBin Meng 3*ade8127aSBin Meng/include/ "skeleton.dtsi" 4*ade8127aSBin Meng/include/ "serial.dtsi" 5*ade8127aSBin Meng 6*ade8127aSBin Meng/ { 7*ade8127aSBin Meng model = "Google Link"; 8*ade8127aSBin Meng compatible = "google,link", "intel,celeron-ivybridge"; 9*ade8127aSBin Meng 10*ade8127aSBin Meng config { 11*ade8127aSBin Meng silent_console = <0>; 12*ade8127aSBin Meng }; 13*ade8127aSBin Meng 14*ade8127aSBin Meng gpioa { 15*ade8127aSBin Meng compatible = "intel,ich6-gpio"; 16*ade8127aSBin Meng u-boot,dm-pre-reloc; 17*ade8127aSBin Meng reg = <0 0x10>; 18*ade8127aSBin Meng bank-name = "A"; 19*ade8127aSBin Meng }; 20*ade8127aSBin Meng 21*ade8127aSBin Meng gpiob { 22*ade8127aSBin Meng compatible = "intel,ich6-gpio"; 23*ade8127aSBin Meng u-boot,dm-pre-reloc; 24*ade8127aSBin Meng reg = <0x30 0x10>; 25*ade8127aSBin Meng bank-name = "B"; 26*ade8127aSBin Meng }; 27*ade8127aSBin Meng 28*ade8127aSBin Meng gpioc { 29*ade8127aSBin Meng compatible = "intel,ich6-gpio"; 30*ade8127aSBin Meng u-boot,dm-pre-reloc; 31*ade8127aSBin Meng reg = <0x40 0x10>; 32*ade8127aSBin Meng bank-name = "C"; 33*ade8127aSBin Meng }; 34*ade8127aSBin Meng 35*ade8127aSBin Meng chosen { 36*ade8127aSBin Meng stdout-path = "/serial"; 37*ade8127aSBin Meng }; 38*ade8127aSBin Meng 39*ade8127aSBin Meng spd { 40*ade8127aSBin Meng compatible = "memory-spd"; 41*ade8127aSBin Meng #address-cells = <1>; 42*ade8127aSBin Meng #size-cells = <0>; 43*ade8127aSBin Meng elpida_4Gb_1600_x16 { 44*ade8127aSBin Meng reg = <0>; 45*ade8127aSBin Meng data = [92 10 0b 03 04 19 02 02 46*ade8127aSBin Meng 03 52 01 08 0a 00 fe 00 47*ade8127aSBin Meng 69 78 69 3c 69 11 18 81 48*ade8127aSBin Meng 20 08 3c 3c 01 40 83 81 49*ade8127aSBin Meng 00 00 00 00 00 00 00 00 50*ade8127aSBin Meng 00 00 00 00 00 00 00 00 51*ade8127aSBin Meng 00 00 00 00 00 00 00 00 52*ade8127aSBin Meng 00 00 00 00 0f 11 42 00 53*ade8127aSBin Meng 00 00 00 00 00 00 00 00 54*ade8127aSBin Meng 00 00 00 00 00 00 00 00 55*ade8127aSBin Meng 00 00 00 00 00 00 00 00 56*ade8127aSBin Meng 00 00 00 00 00 00 00 00 57*ade8127aSBin Meng 00 00 00 00 00 00 00 00 58*ade8127aSBin Meng 00 00 00 00 00 00 00 00 59*ade8127aSBin Meng 00 00 00 00 00 02 fe 00 60*ade8127aSBin Meng 11 52 00 00 00 07 7f 37 61*ade8127aSBin Meng 45 42 4a 32 30 55 47 36 62*ade8127aSBin Meng 45 42 55 30 2d 47 4e 2d 63*ade8127aSBin Meng 46 20 30 20 02 fe 00 00 64*ade8127aSBin Meng 00 00 00 00 00 00 00 00 65*ade8127aSBin Meng 00 00 00 00 00 00 00 00 66*ade8127aSBin Meng 00 00 00 00 00 00 00 00 67*ade8127aSBin Meng 00 00 00 00 00 00 00 00 68*ade8127aSBin Meng 00 00 00 00 00 00 00 00 69*ade8127aSBin Meng 00 00 00 00 00 00 00 00 70*ade8127aSBin Meng 00 00 00 00 00 00 00 00 71*ade8127aSBin Meng 00 00 00 00 00 00 00 00 72*ade8127aSBin Meng 00 00 00 00 00 00 00 00 73*ade8127aSBin Meng 00 00 00 00 00 00 00 00 74*ade8127aSBin Meng 00 00 00 00 00 00 00 00 75*ade8127aSBin Meng 00 00 00 00 00 00 00 00 76*ade8127aSBin Meng 00 00 00 00 00 00 00 00]; 77*ade8127aSBin Meng }; 78*ade8127aSBin Meng samsung_4Gb_1600_1.35v_x16 { 79*ade8127aSBin Meng reg = <1>; 80*ade8127aSBin Meng data = [92 11 0b 03 04 19 02 02 81*ade8127aSBin Meng 03 11 01 08 0a 00 fe 00 82*ade8127aSBin Meng 69 78 69 3c 69 11 18 81 83*ade8127aSBin Meng f0 0a 3c 3c 01 40 83 01 84*ade8127aSBin Meng 00 80 00 00 00 00 00 00 85*ade8127aSBin Meng 00 00 00 00 00 00 00 00 86*ade8127aSBin Meng 00 00 00 00 00 00 00 00 87*ade8127aSBin Meng 00 00 00 00 0f 11 02 00 88*ade8127aSBin Meng 00 00 00 00 00 00 00 00 89*ade8127aSBin Meng 00 00 00 00 00 00 00 00 90*ade8127aSBin Meng 00 00 00 00 00 00 00 00 91*ade8127aSBin Meng 00 00 00 00 00 00 00 00 92*ade8127aSBin Meng 00 00 00 00 00 00 00 00 93*ade8127aSBin Meng 00 00 00 00 00 00 00 00 94*ade8127aSBin Meng 00 00 00 00 00 80 ce 01 95*ade8127aSBin Meng 00 00 00 00 00 00 6a 04 96*ade8127aSBin Meng 4d 34 37 31 42 35 36 37 97*ade8127aSBin Meng 34 42 48 30 2d 59 4b 30 98*ade8127aSBin Meng 20 20 00 00 80 ce 00 00 99*ade8127aSBin Meng 00 00 00 00 00 00 00 00 100*ade8127aSBin Meng 00 00 00 00 00 00 00 00 101*ade8127aSBin Meng 00 00 00 00 00 00 00 00 102*ade8127aSBin Meng 00 00 00 00 00 00 00 00 103*ade8127aSBin Meng 00 00 00 00 00 00 00 00 104*ade8127aSBin Meng 00 00 00 00 00 00 00 00 105*ade8127aSBin Meng 00 00 00 00 00 00 00 00 106*ade8127aSBin Meng 00 00 00 00 00 00 00 00 107*ade8127aSBin Meng 00 00 00 00 00 00 00 00 108*ade8127aSBin Meng 00 00 00 00 00 00 00 00 109*ade8127aSBin Meng 00 00 00 00 00 00 00 00 110*ade8127aSBin Meng 00 00 00 00 00 00 00 00 111*ade8127aSBin Meng 00 00 00 00 00 00 00 00]; 112*ade8127aSBin Meng }; 113*ade8127aSBin Meng micron_4Gb_1600_1.35v_x16 { 114*ade8127aSBin Meng reg = <2>; 115*ade8127aSBin Meng data = [92 11 0b 03 04 19 02 02 116*ade8127aSBin Meng 03 11 01 08 0a 00 fe 00 117*ade8127aSBin Meng 69 78 69 3c 69 11 18 81 118*ade8127aSBin Meng 20 08 3c 3c 01 40 83 05 119*ade8127aSBin Meng 00 00 00 00 00 00 00 00 120*ade8127aSBin Meng 00 00 00 00 00 00 00 00 121*ade8127aSBin Meng 00 00 00 00 00 00 00 00 122*ade8127aSBin Meng 00 00 00 00 0f 01 02 00 123*ade8127aSBin Meng 00 00 00 00 00 00 00 00 124*ade8127aSBin Meng 00 00 00 00 00 00 00 00 125*ade8127aSBin Meng 00 00 00 00 00 00 00 00 126*ade8127aSBin Meng 00 00 00 00 00 00 00 00 127*ade8127aSBin Meng 00 00 00 00 00 00 00 00 128*ade8127aSBin Meng 00 00 00 00 00 00 00 00 129*ade8127aSBin Meng 00 00 00 00 00 80 2c 00 130*ade8127aSBin Meng 00 00 00 00 00 00 ad 75 131*ade8127aSBin Meng 34 4b 54 46 32 35 36 36 132*ade8127aSBin Meng 34 48 5a 2d 31 47 36 45 133*ade8127aSBin Meng 31 20 45 31 80 2c 00 00 134*ade8127aSBin Meng 00 00 00 00 00 00 00 00 135*ade8127aSBin Meng 00 00 00 00 00 00 00 00 136*ade8127aSBin Meng 00 00 00 00 00 00 00 00 137*ade8127aSBin Meng ff ff ff ff ff ff ff ff 138*ade8127aSBin Meng ff ff ff ff ff ff ff ff 139*ade8127aSBin Meng ff ff ff ff ff ff ff ff 140*ade8127aSBin Meng ff ff ff ff ff ff ff ff 141*ade8127aSBin Meng ff ff ff ff ff ff ff ff 142*ade8127aSBin Meng ff ff ff ff ff ff ff ff 143*ade8127aSBin Meng ff ff ff ff ff ff ff ff 144*ade8127aSBin Meng ff ff ff ff ff ff ff ff 145*ade8127aSBin Meng ff ff ff ff ff ff ff ff 146*ade8127aSBin Meng ff ff ff ff ff ff ff ff]; 147*ade8127aSBin Meng }; 148*ade8127aSBin Meng }; 149*ade8127aSBin Meng 150*ade8127aSBin Meng spi { 151*ade8127aSBin Meng #address-cells = <1>; 152*ade8127aSBin Meng #size-cells = <0>; 153*ade8127aSBin Meng compatible = "intel,ich9"; 154*ade8127aSBin Meng spi-flash@0 { 155*ade8127aSBin Meng reg = <0>; 156*ade8127aSBin Meng compatible = "winbond,w25q64", "spi-flash"; 157*ade8127aSBin Meng memory-map = <0xff800000 0x00800000>; 158*ade8127aSBin Meng }; 159*ade8127aSBin Meng }; 160*ade8127aSBin Meng 161*ade8127aSBin Meng pci { 162*ade8127aSBin Meng sata { 163*ade8127aSBin Meng compatible = "intel,pantherpoint-ahci"; 164*ade8127aSBin Meng intel,sata-mode = "ahci"; 165*ade8127aSBin Meng intel,sata-port-map = <1>; 166*ade8127aSBin Meng intel,sata-port0-gen3-tx = <0x00880a7f>; 167*ade8127aSBin Meng }; 168*ade8127aSBin Meng 169*ade8127aSBin Meng gma { 170*ade8127aSBin Meng compatible = "intel,gma"; 171*ade8127aSBin Meng intel,dp_hotplug = <0 0 0x06>; 172*ade8127aSBin Meng intel,panel-port-select = <1>; 173*ade8127aSBin Meng intel,panel-power-cycle-delay = <6>; 174*ade8127aSBin Meng intel,panel-power-up-delay = <2000>; 175*ade8127aSBin Meng intel,panel-power-down-delay = <500>; 176*ade8127aSBin Meng intel,panel-power-backlight-on-delay = <2000>; 177*ade8127aSBin Meng intel,panel-power-backlight-off-delay = <2000>; 178*ade8127aSBin Meng intel,cpu-backlight = <0x00000200>; 179*ade8127aSBin Meng intel,pch-backlight = <0x04000000>; 180*ade8127aSBin Meng }; 181*ade8127aSBin Meng 182*ade8127aSBin Meng lpc { 183*ade8127aSBin Meng compatible = "intel,lpc"; 184*ade8127aSBin Meng #address-cells = <1>; 185*ade8127aSBin Meng #size-cells = <1>; 186*ade8127aSBin Meng gen-dec = <0x800 0xfc 0x900 0xfc>; 187*ade8127aSBin Meng intel,gen-dec = <0x800 0xfc 0x900 0xfc>; 188*ade8127aSBin Meng intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b 189*ade8127aSBin Meng 0x80 0x80 0x80 0x80>; 190*ade8127aSBin Meng intel,gpi-routing = <0 0 0 0 0 0 0 2 191*ade8127aSBin Meng 1 0 0 0 0 0 0 0>; 192*ade8127aSBin Meng /* Enable EC SMI source */ 193*ade8127aSBin Meng intel,alt-gp-smi-enable = <0x0100>; 194*ade8127aSBin Meng 195*ade8127aSBin Meng cros-ec@200 { 196*ade8127aSBin Meng compatible = "google,cros-ec"; 197*ade8127aSBin Meng reg = <0x204 1 0x200 1 0x880 0x80>; 198*ade8127aSBin Meng 199*ade8127aSBin Meng /* Describes the flash memory within the EC */ 200*ade8127aSBin Meng #address-cells = <1>; 201*ade8127aSBin Meng #size-cells = <1>; 202*ade8127aSBin Meng flash@8000000 { 203*ade8127aSBin Meng reg = <0x08000000 0x20000>; 204*ade8127aSBin Meng erase-value = <0xff>; 205*ade8127aSBin Meng }; 206*ade8127aSBin Meng }; 207*ade8127aSBin Meng }; 208*ade8127aSBin Meng }; 209*ade8127aSBin Meng 210*ade8127aSBin Meng microcode { 211*ade8127aSBin Meng update@0 { 212*ade8127aSBin Meng#include "microcode/m12306a9_0000001b.dtsi" 213*ade8127aSBin Meng }; 214*ade8127aSBin Meng }; 215*ade8127aSBin Meng 216*ade8127aSBin Meng}; 217