1/* 2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/gpio/x86-gpio.h> 10#include <dt-bindings/interrupt-router/intel-irq.h> 11 12/include/ "skeleton.dtsi" 13/include/ "serial.dtsi" 14/include/ "rtc.dtsi" 15 16/ { 17 model = "Intel Bayley Bay"; 18 compatible = "intel,bayleybay", "intel,baytrail"; 19 20 aliases { 21 serial0 = &serial; 22 spi0 = "/spi"; 23 }; 24 25 config { 26 silent_console = <0>; 27 }; 28 29 chosen { 30 stdout-path = "/serial"; 31 }; 32 33 cpus { 34 #address-cells = <1>; 35 #size-cells = <0>; 36 37 cpu@0 { 38 device_type = "cpu"; 39 compatible = "intel,baytrail-cpu"; 40 reg = <0>; 41 intel,apic-id = <0>; 42 }; 43 44 cpu@1 { 45 device_type = "cpu"; 46 compatible = "intel,baytrail-cpu"; 47 reg = <1>; 48 intel,apic-id = <2>; 49 }; 50 51 cpu@2 { 52 device_type = "cpu"; 53 compatible = "intel,baytrail-cpu"; 54 reg = <2>; 55 intel,apic-id = <4>; 56 }; 57 58 cpu@3 { 59 device_type = "cpu"; 60 compatible = "intel,baytrail-cpu"; 61 reg = <3>; 62 intel,apic-id = <6>; 63 }; 64 }; 65 66 spi { 67 #address-cells = <1>; 68 #size-cells = <0>; 69 compatible = "intel,ich-spi"; 70 spi-flash@0 { 71 #address-cells = <1>; 72 #size-cells = <1>; 73 reg = <0>; 74 compatible = "winbond,w25q64dw", "spi-flash"; 75 memory-map = <0xff800000 0x00800000>; 76 rw-mrc-cache { 77 label = "rw-mrc-cache"; 78 reg = <0x006e0000 0x00010000>; 79 }; 80 }; 81 }; 82 83 gpioa { 84 compatible = "intel,ich6-gpio"; 85 u-boot,dm-pre-reloc; 86 reg = <0 0x20>; 87 bank-name = "A"; 88 }; 89 90 gpiob { 91 compatible = "intel,ich6-gpio"; 92 u-boot,dm-pre-reloc; 93 reg = <0x20 0x20>; 94 bank-name = "B"; 95 }; 96 97 gpioc { 98 compatible = "intel,ich6-gpio"; 99 u-boot,dm-pre-reloc; 100 reg = <0x40 0x20>; 101 bank-name = "C"; 102 }; 103 104 gpiod { 105 compatible = "intel,ich6-gpio"; 106 u-boot,dm-pre-reloc; 107 reg = <0x60 0x20>; 108 bank-name = "D"; 109 }; 110 111 gpioe { 112 compatible = "intel,ich6-gpio"; 113 u-boot,dm-pre-reloc; 114 reg = <0x80 0x20>; 115 bank-name = "E"; 116 }; 117 118 gpiof { 119 compatible = "intel,ich6-gpio"; 120 u-boot,dm-pre-reloc; 121 reg = <0xA0 0x20>; 122 bank-name = "F"; 123 }; 124 125 pci { 126 compatible = "pci-x86"; 127 #address-cells = <3>; 128 #size-cells = <2>; 129 u-boot,dm-pre-reloc; 130 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000 131 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 132 0x01000000 0x0 0x2000 0x2000 0 0xe000>; 133 134 irq-router@1f,0 { 135 reg = <0x0000f800 0 0 0 0>; 136 compatible = "intel,irq-router"; 137 intel,pirq-config = "ibase"; 138 intel,ibase-offset = <0x50>; 139 intel,pirq-link = <8 8>; 140 intel,pirq-mask = <0xdee0>; 141 intel,pirq-routing = < 142 /* BayTrail PCI devices */ 143 PCI_BDF(0, 2, 0) INTA PIRQA 144 PCI_BDF(0, 3, 0) INTA PIRQA 145 PCI_BDF(0, 16, 0) INTA PIRQA 146 PCI_BDF(0, 17, 0) INTA PIRQA 147 PCI_BDF(0, 18, 0) INTA PIRQA 148 PCI_BDF(0, 19, 0) INTA PIRQA 149 PCI_BDF(0, 20, 0) INTA PIRQA 150 PCI_BDF(0, 21, 0) INTA PIRQA 151 PCI_BDF(0, 22, 0) INTA PIRQA 152 PCI_BDF(0, 23, 0) INTA PIRQA 153 PCI_BDF(0, 24, 0) INTA PIRQA 154 PCI_BDF(0, 24, 1) INTC PIRQC 155 PCI_BDF(0, 24, 2) INTD PIRQD 156 PCI_BDF(0, 24, 3) INTB PIRQB 157 PCI_BDF(0, 24, 4) INTA PIRQA 158 PCI_BDF(0, 24, 5) INTC PIRQC 159 PCI_BDF(0, 24, 6) INTD PIRQD 160 PCI_BDF(0, 24, 7) INTB PIRQB 161 PCI_BDF(0, 26, 0) INTA PIRQA 162 PCI_BDF(0, 27, 0) INTA PIRQA 163 PCI_BDF(0, 28, 0) INTA PIRQA 164 PCI_BDF(0, 28, 1) INTB PIRQB 165 PCI_BDF(0, 28, 2) INTC PIRQC 166 PCI_BDF(0, 28, 3) INTD PIRQD 167 PCI_BDF(0, 29, 0) INTA PIRQA 168 PCI_BDF(0, 30, 0) INTA PIRQA 169 PCI_BDF(0, 30, 1) INTD PIRQD 170 PCI_BDF(0, 30, 2) INTB PIRQB 171 PCI_BDF(0, 30, 3) INTC PIRQC 172 PCI_BDF(0, 30, 4) INTD PIRQD 173 PCI_BDF(0, 30, 5) INTB PIRQB 174 PCI_BDF(0, 31, 3) INTB PIRQB 175 176 /* PCIe root ports downstream interrupts */ 177 PCI_BDF(1, 0, 0) INTA PIRQA 178 PCI_BDF(1, 0, 0) INTB PIRQB 179 PCI_BDF(1, 0, 0) INTC PIRQC 180 PCI_BDF(1, 0, 0) INTD PIRQD 181 PCI_BDF(2, 0, 0) INTA PIRQB 182 PCI_BDF(2, 0, 0) INTB PIRQC 183 PCI_BDF(2, 0, 0) INTC PIRQD 184 PCI_BDF(2, 0, 0) INTD PIRQA 185 PCI_BDF(3, 0, 0) INTA PIRQC 186 PCI_BDF(3, 0, 0) INTB PIRQD 187 PCI_BDF(3, 0, 0) INTC PIRQA 188 PCI_BDF(3, 0, 0) INTD PIRQB 189 PCI_BDF(4, 0, 0) INTA PIRQD 190 PCI_BDF(4, 0, 0) INTB PIRQA 191 PCI_BDF(4, 0, 0) INTC PIRQB 192 PCI_BDF(4, 0, 0) INTD PIRQC 193 >; 194 }; 195 }; 196 197 fsp { 198 compatible = "intel,baytrail-fsp"; 199 fsp,mrc-init-tseg-size = <0>; 200 fsp,mrc-init-mmio-size = <0x800>; 201 fsp,mrc-init-spd-addr1 = <0xa0>; 202 fsp,mrc-init-spd-addr2 = <0xa2>; 203 fsp,emmc-boot-mode = <2>; 204 fsp,enable-sdio; 205 fsp,enable-sdcard; 206 fsp,enable-hsuart1; 207 fsp,enable-spi; 208 fsp,enable-sata; 209 fsp,sata-mode = <1>; 210 fsp,enable-lpe; 211 fsp,lpss-sio-enable-pci-mode; 212 fsp,enable-dma0; 213 fsp,enable-dma1; 214 fsp,enable-i2c0; 215 fsp,enable-i2c1; 216 fsp,enable-i2c2; 217 fsp,enable-i2c3; 218 fsp,enable-i2c4; 219 fsp,enable-i2c5; 220 fsp,enable-i2c6; 221 fsp,enable-pwm0; 222 fsp,enable-pwm1; 223 fsp,igd-dvmt50-pre-alloc = <2>; 224 fsp,aperture-size = <2>; 225 fsp,gtt-size = <2>; 226 fsp,serial-debug-port-address = <0x3f8>; 227 fsp,serial-debug-port-type = <1>; 228 fsp,scc-enable-pci-mode; 229 fsp,os-selection = <4>; 230 fsp,emmc45-ddr50-enabled; 231 fsp,emmc45-retune-timer-value = <8>; 232 fsp,enable-igd; 233 }; 234 235 microcode { 236 update@0 { 237#include "microcode/m0230671117.dtsi" 238 }; 239 update@1 { 240#include "microcode/m0130673322.dtsi" 241 }; 242 update@2 { 243#include "microcode/m0130679901.dtsi" 244 }; 245 }; 246 247}; 248