1/* 2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/gpio/x86-gpio.h> 10#include <dt-bindings/interrupt-router/intel-irq.h> 11 12/include/ "skeleton.dtsi" 13/include/ "keyboard.dtsi" 14/include/ "serial.dtsi" 15/include/ "rtc.dtsi" 16 17/ { 18 model = "Intel Bayley Bay"; 19 compatible = "intel,bayleybay", "intel,baytrail"; 20 21 aliases { 22 serial0 = &serial; 23 spi0 = "/spi"; 24 }; 25 26 config { 27 silent_console = <0>; 28 }; 29 30 chosen { 31 stdout-path = "/serial"; 32 }; 33 34 cpus { 35 #address-cells = <1>; 36 #size-cells = <0>; 37 38 cpu@0 { 39 device_type = "cpu"; 40 compatible = "intel,baytrail-cpu"; 41 reg = <0>; 42 intel,apic-id = <0>; 43 }; 44 45 cpu@1 { 46 device_type = "cpu"; 47 compatible = "intel,baytrail-cpu"; 48 reg = <1>; 49 intel,apic-id = <2>; 50 }; 51 52 cpu@2 { 53 device_type = "cpu"; 54 compatible = "intel,baytrail-cpu"; 55 reg = <2>; 56 intel,apic-id = <4>; 57 }; 58 59 cpu@3 { 60 device_type = "cpu"; 61 compatible = "intel,baytrail-cpu"; 62 reg = <3>; 63 intel,apic-id = <6>; 64 }; 65 }; 66 67 spi { 68 #address-cells = <1>; 69 #size-cells = <0>; 70 compatible = "intel,ich-spi"; 71 spi-flash@0 { 72 #address-cells = <1>; 73 #size-cells = <1>; 74 reg = <0>; 75 compatible = "winbond,w25q64dw", "spi-flash"; 76 memory-map = <0xff800000 0x00800000>; 77 rw-mrc-cache { 78 label = "rw-mrc-cache"; 79 reg = <0x006e0000 0x00010000>; 80 }; 81 }; 82 }; 83 84 gpioa { 85 compatible = "intel,ich6-gpio"; 86 u-boot,dm-pre-reloc; 87 reg = <0 0x20>; 88 bank-name = "A"; 89 }; 90 91 gpiob { 92 compatible = "intel,ich6-gpio"; 93 u-boot,dm-pre-reloc; 94 reg = <0x20 0x20>; 95 bank-name = "B"; 96 }; 97 98 gpioc { 99 compatible = "intel,ich6-gpio"; 100 u-boot,dm-pre-reloc; 101 reg = <0x40 0x20>; 102 bank-name = "C"; 103 }; 104 105 gpiod { 106 compatible = "intel,ich6-gpio"; 107 u-boot,dm-pre-reloc; 108 reg = <0x60 0x20>; 109 bank-name = "D"; 110 }; 111 112 gpioe { 113 compatible = "intel,ich6-gpio"; 114 u-boot,dm-pre-reloc; 115 reg = <0x80 0x20>; 116 bank-name = "E"; 117 }; 118 119 gpiof { 120 compatible = "intel,ich6-gpio"; 121 u-boot,dm-pre-reloc; 122 reg = <0xA0 0x20>; 123 bank-name = "F"; 124 }; 125 126 pci { 127 compatible = "pci-x86"; 128 #address-cells = <3>; 129 #size-cells = <2>; 130 u-boot,dm-pre-reloc; 131 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000 132 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 133 0x01000000 0x0 0x2000 0x2000 0 0xe000>; 134 135 irq-router@1f,0 { 136 reg = <0x0000f800 0 0 0 0>; 137 compatible = "intel,irq-router"; 138 intel,pirq-config = "ibase"; 139 intel,ibase-offset = <0x50>; 140 intel,pirq-link = <8 8>; 141 intel,pirq-mask = <0xdee0>; 142 intel,pirq-routing = < 143 /* BayTrail PCI devices */ 144 PCI_BDF(0, 2, 0) INTA PIRQA 145 PCI_BDF(0, 3, 0) INTA PIRQA 146 PCI_BDF(0, 16, 0) INTA PIRQA 147 PCI_BDF(0, 17, 0) INTA PIRQA 148 PCI_BDF(0, 18, 0) INTA PIRQA 149 PCI_BDF(0, 19, 0) INTA PIRQA 150 PCI_BDF(0, 20, 0) INTA PIRQA 151 PCI_BDF(0, 21, 0) INTA PIRQA 152 PCI_BDF(0, 22, 0) INTA PIRQA 153 PCI_BDF(0, 23, 0) INTA PIRQA 154 PCI_BDF(0, 24, 0) INTA PIRQA 155 PCI_BDF(0, 24, 1) INTC PIRQC 156 PCI_BDF(0, 24, 2) INTD PIRQD 157 PCI_BDF(0, 24, 3) INTB PIRQB 158 PCI_BDF(0, 24, 4) INTA PIRQA 159 PCI_BDF(0, 24, 5) INTC PIRQC 160 PCI_BDF(0, 24, 6) INTD PIRQD 161 PCI_BDF(0, 24, 7) INTB PIRQB 162 PCI_BDF(0, 26, 0) INTA PIRQA 163 PCI_BDF(0, 27, 0) INTA PIRQA 164 PCI_BDF(0, 28, 0) INTA PIRQA 165 PCI_BDF(0, 28, 1) INTB PIRQB 166 PCI_BDF(0, 28, 2) INTC PIRQC 167 PCI_BDF(0, 28, 3) INTD PIRQD 168 PCI_BDF(0, 29, 0) INTA PIRQA 169 PCI_BDF(0, 30, 0) INTA PIRQA 170 PCI_BDF(0, 30, 1) INTD PIRQD 171 PCI_BDF(0, 30, 2) INTB PIRQB 172 PCI_BDF(0, 30, 3) INTC PIRQC 173 PCI_BDF(0, 30, 4) INTD PIRQD 174 PCI_BDF(0, 30, 5) INTB PIRQB 175 PCI_BDF(0, 31, 3) INTB PIRQB 176 177 /* PCIe root ports downstream interrupts */ 178 PCI_BDF(1, 0, 0) INTA PIRQA 179 PCI_BDF(1, 0, 0) INTB PIRQB 180 PCI_BDF(1, 0, 0) INTC PIRQC 181 PCI_BDF(1, 0, 0) INTD PIRQD 182 PCI_BDF(2, 0, 0) INTA PIRQB 183 PCI_BDF(2, 0, 0) INTB PIRQC 184 PCI_BDF(2, 0, 0) INTC PIRQD 185 PCI_BDF(2, 0, 0) INTD PIRQA 186 PCI_BDF(3, 0, 0) INTA PIRQC 187 PCI_BDF(3, 0, 0) INTB PIRQD 188 PCI_BDF(3, 0, 0) INTC PIRQA 189 PCI_BDF(3, 0, 0) INTD PIRQB 190 PCI_BDF(4, 0, 0) INTA PIRQD 191 PCI_BDF(4, 0, 0) INTB PIRQA 192 PCI_BDF(4, 0, 0) INTC PIRQB 193 PCI_BDF(4, 0, 0) INTD PIRQC 194 >; 195 }; 196 }; 197 198 fsp { 199 compatible = "intel,baytrail-fsp"; 200 fsp,mrc-init-tseg-size = <0>; 201 fsp,mrc-init-mmio-size = <0x800>; 202 fsp,mrc-init-spd-addr1 = <0xa0>; 203 fsp,mrc-init-spd-addr2 = <0xa2>; 204 fsp,emmc-boot-mode = <2>; 205 fsp,enable-sdio; 206 fsp,enable-sdcard; 207 fsp,enable-hsuart1; 208 fsp,enable-spi; 209 fsp,enable-sata; 210 fsp,sata-mode = <1>; 211 fsp,enable-lpe; 212 fsp,lpss-sio-enable-pci-mode; 213 fsp,enable-dma0; 214 fsp,enable-dma1; 215 fsp,enable-i2c0; 216 fsp,enable-i2c1; 217 fsp,enable-i2c2; 218 fsp,enable-i2c3; 219 fsp,enable-i2c4; 220 fsp,enable-i2c5; 221 fsp,enable-i2c6; 222 fsp,enable-pwm0; 223 fsp,enable-pwm1; 224 fsp,igd-dvmt50-pre-alloc = <2>; 225 fsp,aperture-size = <2>; 226 fsp,gtt-size = <2>; 227 fsp,serial-debug-port-address = <0x3f8>; 228 fsp,serial-debug-port-type = <1>; 229 fsp,scc-enable-pci-mode; 230 fsp,os-selection = <4>; 231 fsp,emmc45-ddr50-enabled; 232 fsp,emmc45-retune-timer-value = <8>; 233 fsp,enable-igd; 234 }; 235 236 microcode { 237 update@0 { 238#include "microcode/m0230671117.dtsi" 239 }; 240 update@1 { 241#include "microcode/m0130673322.dtsi" 242 }; 243 update@2 { 244#include "microcode/m0130679901.dtsi" 245 }; 246 }; 247 248}; 249