1/* 2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/gpio/x86-gpio.h> 10#include <dt-bindings/interrupt-router/intel-irq.h> 11 12/include/ "skeleton.dtsi" 13/include/ "keyboard.dtsi" 14/include/ "serial.dtsi" 15/include/ "rtc.dtsi" 16/include/ "tsc_timer.dtsi" 17 18/ { 19 model = "Intel Bayley Bay"; 20 compatible = "intel,bayleybay", "intel,baytrail"; 21 22 aliases { 23 serial0 = &serial; 24 spi0 = "/spi"; 25 }; 26 27 config { 28 silent_console = <0>; 29 }; 30 31 chosen { 32 stdout-path = "/serial"; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 cpu@0 { 40 device_type = "cpu"; 41 compatible = "intel,baytrail-cpu"; 42 reg = <0>; 43 intel,apic-id = <0>; 44 }; 45 46 cpu@1 { 47 device_type = "cpu"; 48 compatible = "intel,baytrail-cpu"; 49 reg = <1>; 50 intel,apic-id = <2>; 51 }; 52 53 cpu@2 { 54 device_type = "cpu"; 55 compatible = "intel,baytrail-cpu"; 56 reg = <2>; 57 intel,apic-id = <4>; 58 }; 59 60 cpu@3 { 61 device_type = "cpu"; 62 compatible = "intel,baytrail-cpu"; 63 reg = <3>; 64 intel,apic-id = <6>; 65 }; 66 }; 67 68 spi { 69 #address-cells = <1>; 70 #size-cells = <0>; 71 compatible = "intel,ich-spi"; 72 spi-flash@0 { 73 #address-cells = <1>; 74 #size-cells = <1>; 75 reg = <0>; 76 compatible = "winbond,w25q64dw", "spi-flash"; 77 memory-map = <0xff800000 0x00800000>; 78 rw-mrc-cache { 79 label = "rw-mrc-cache"; 80 reg = <0x006e0000 0x00010000>; 81 }; 82 }; 83 }; 84 85 gpioa { 86 compatible = "intel,ich6-gpio"; 87 u-boot,dm-pre-reloc; 88 reg = <0 0x20>; 89 bank-name = "A"; 90 }; 91 92 gpiob { 93 compatible = "intel,ich6-gpio"; 94 u-boot,dm-pre-reloc; 95 reg = <0x20 0x20>; 96 bank-name = "B"; 97 }; 98 99 gpioc { 100 compatible = "intel,ich6-gpio"; 101 u-boot,dm-pre-reloc; 102 reg = <0x40 0x20>; 103 bank-name = "C"; 104 }; 105 106 gpiod { 107 compatible = "intel,ich6-gpio"; 108 u-boot,dm-pre-reloc; 109 reg = <0x60 0x20>; 110 bank-name = "D"; 111 }; 112 113 gpioe { 114 compatible = "intel,ich6-gpio"; 115 u-boot,dm-pre-reloc; 116 reg = <0x80 0x20>; 117 bank-name = "E"; 118 }; 119 120 gpiof { 121 compatible = "intel,ich6-gpio"; 122 u-boot,dm-pre-reloc; 123 reg = <0xA0 0x20>; 124 bank-name = "F"; 125 }; 126 127 pci { 128 compatible = "pci-x86"; 129 #address-cells = <3>; 130 #size-cells = <2>; 131 u-boot,dm-pre-reloc; 132 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000 133 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 134 0x01000000 0x0 0x2000 0x2000 0 0xe000>; 135 136 irq-router@1f,0 { 137 reg = <0x0000f800 0 0 0 0>; 138 compatible = "intel,irq-router"; 139 intel,pirq-config = "ibase"; 140 intel,ibase-offset = <0x50>; 141 intel,pirq-link = <8 8>; 142 intel,pirq-mask = <0xdee0>; 143 intel,pirq-routing = < 144 /* BayTrail PCI devices */ 145 PCI_BDF(0, 2, 0) INTA PIRQA 146 PCI_BDF(0, 3, 0) INTA PIRQA 147 PCI_BDF(0, 16, 0) INTA PIRQA 148 PCI_BDF(0, 17, 0) INTA PIRQA 149 PCI_BDF(0, 18, 0) INTA PIRQA 150 PCI_BDF(0, 19, 0) INTA PIRQA 151 PCI_BDF(0, 20, 0) INTA PIRQA 152 PCI_BDF(0, 21, 0) INTA PIRQA 153 PCI_BDF(0, 22, 0) INTA PIRQA 154 PCI_BDF(0, 23, 0) INTA PIRQA 155 PCI_BDF(0, 24, 0) INTA PIRQA 156 PCI_BDF(0, 24, 1) INTC PIRQC 157 PCI_BDF(0, 24, 2) INTD PIRQD 158 PCI_BDF(0, 24, 3) INTB PIRQB 159 PCI_BDF(0, 24, 4) INTA PIRQA 160 PCI_BDF(0, 24, 5) INTC PIRQC 161 PCI_BDF(0, 24, 6) INTD PIRQD 162 PCI_BDF(0, 24, 7) INTB PIRQB 163 PCI_BDF(0, 26, 0) INTA PIRQA 164 PCI_BDF(0, 27, 0) INTA PIRQA 165 PCI_BDF(0, 28, 0) INTA PIRQA 166 PCI_BDF(0, 28, 1) INTB PIRQB 167 PCI_BDF(0, 28, 2) INTC PIRQC 168 PCI_BDF(0, 28, 3) INTD PIRQD 169 PCI_BDF(0, 29, 0) INTA PIRQA 170 PCI_BDF(0, 30, 0) INTA PIRQA 171 PCI_BDF(0, 30, 1) INTD PIRQD 172 PCI_BDF(0, 30, 2) INTB PIRQB 173 PCI_BDF(0, 30, 3) INTC PIRQC 174 PCI_BDF(0, 30, 4) INTD PIRQD 175 PCI_BDF(0, 30, 5) INTB PIRQB 176 PCI_BDF(0, 31, 3) INTB PIRQB 177 178 /* PCIe root ports downstream interrupts */ 179 PCI_BDF(1, 0, 0) INTA PIRQA 180 PCI_BDF(1, 0, 0) INTB PIRQB 181 PCI_BDF(1, 0, 0) INTC PIRQC 182 PCI_BDF(1, 0, 0) INTD PIRQD 183 PCI_BDF(2, 0, 0) INTA PIRQB 184 PCI_BDF(2, 0, 0) INTB PIRQC 185 PCI_BDF(2, 0, 0) INTC PIRQD 186 PCI_BDF(2, 0, 0) INTD PIRQA 187 PCI_BDF(3, 0, 0) INTA PIRQC 188 PCI_BDF(3, 0, 0) INTB PIRQD 189 PCI_BDF(3, 0, 0) INTC PIRQA 190 PCI_BDF(3, 0, 0) INTD PIRQB 191 PCI_BDF(4, 0, 0) INTA PIRQD 192 PCI_BDF(4, 0, 0) INTB PIRQA 193 PCI_BDF(4, 0, 0) INTC PIRQB 194 PCI_BDF(4, 0, 0) INTD PIRQC 195 >; 196 }; 197 }; 198 199 fsp { 200 compatible = "intel,baytrail-fsp"; 201 fsp,mrc-init-tseg-size = <0>; 202 fsp,mrc-init-mmio-size = <0x800>; 203 fsp,mrc-init-spd-addr1 = <0xa0>; 204 fsp,mrc-init-spd-addr2 = <0xa2>; 205 fsp,emmc-boot-mode = <2>; 206 fsp,enable-sdio; 207 fsp,enable-sdcard; 208 fsp,enable-hsuart1; 209 fsp,enable-spi; 210 fsp,enable-sata; 211 fsp,sata-mode = <1>; 212 fsp,enable-lpe; 213 fsp,lpss-sio-enable-pci-mode; 214 fsp,enable-dma0; 215 fsp,enable-dma1; 216 fsp,enable-i2c0; 217 fsp,enable-i2c1; 218 fsp,enable-i2c2; 219 fsp,enable-i2c3; 220 fsp,enable-i2c4; 221 fsp,enable-i2c5; 222 fsp,enable-i2c6; 223 fsp,enable-pwm0; 224 fsp,enable-pwm1; 225 fsp,igd-dvmt50-pre-alloc = <2>; 226 fsp,aperture-size = <2>; 227 fsp,gtt-size = <2>; 228 fsp,serial-debug-port-address = <0x3f8>; 229 fsp,serial-debug-port-type = <1>; 230 fsp,scc-enable-pci-mode; 231 fsp,os-selection = <4>; 232 fsp,emmc45-ddr50-enabled; 233 fsp,emmc45-retune-timer-value = <8>; 234 fsp,enable-igd; 235 }; 236 237 microcode { 238 update@0 { 239#include "microcode/m0230671117.dtsi" 240 }; 241 update@1 { 242#include "microcode/m0130673322.dtsi" 243 }; 244 update@2 { 245#include "microcode/m0130679901.dtsi" 246 }; 247 }; 248 249}; 250