1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 4 */ 5 6/dts-v1/; 7 8#include <asm/arch-baytrail/fsp/fsp_configs.h> 9#include <dt-bindings/gpio/x86-gpio.h> 10#include <dt-bindings/interrupt-router/intel-irq.h> 11 12/include/ "skeleton.dtsi" 13/include/ "keyboard.dtsi" 14/include/ "serial.dtsi" 15/include/ "reset.dtsi" 16/include/ "rtc.dtsi" 17/include/ "tsc_timer.dtsi" 18 19/ { 20 model = "Intel Bayley Bay"; 21 compatible = "intel,bayleybay", "intel,baytrail"; 22 23 aliases { 24 serial0 = &serial; 25 spi0 = &spi; 26 }; 27 28 config { 29 silent_console = <0>; 30 }; 31 32 chosen { 33 stdout-path = "/serial"; 34 }; 35 36 cpus { 37 #address-cells = <1>; 38 #size-cells = <0>; 39 40 cpu@0 { 41 device_type = "cpu"; 42 compatible = "intel,baytrail-cpu"; 43 reg = <0>; 44 intel,apic-id = <0>; 45 }; 46 47 cpu@1 { 48 device_type = "cpu"; 49 compatible = "intel,baytrail-cpu"; 50 reg = <1>; 51 intel,apic-id = <2>; 52 }; 53 54 cpu@2 { 55 device_type = "cpu"; 56 compatible = "intel,baytrail-cpu"; 57 reg = <2>; 58 intel,apic-id = <4>; 59 }; 60 61 cpu@3 { 62 device_type = "cpu"; 63 compatible = "intel,baytrail-cpu"; 64 reg = <3>; 65 intel,apic-id = <6>; 66 }; 67 }; 68 69 pch_pinctrl { 70 compatible = "intel,x86-pinctrl"; 71 reg = <0 0>; 72 73 /* 74 * As of today, the latest version FSP (gold4) for BayTrail 75 * misses the PAD configuration of the SD controller's Card 76 * Detect signal. The default PAD value for the CD pin sets 77 * the pin to work in GPIO mode, which causes card detect 78 * status cannot be reflected by the Present State register 79 * in the SD controller (bit 16 & bit 18 are always zero). 80 * 81 * Configure this pin to function 1 (SD controller). 82 */ 83 sdmmc3_cd@0 { 84 pad-offset = <0x3a0>; 85 mode-func = <1>; 86 }; 87 }; 88 89 pci { 90 compatible = "pci-x86"; 91 #address-cells = <3>; 92 #size-cells = <2>; 93 u-boot,dm-pre-reloc; 94 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000 95 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 96 0x01000000 0x0 0x2000 0x2000 0 0xe000>; 97 98 pch@1f,0 { 99 reg = <0x0000f800 0 0 0 0>; 100 compatible = "intel,pch9"; 101 #address-cells = <1>; 102 #size-cells = <1>; 103 104 irq-router { 105 compatible = "intel,irq-router"; 106 intel,pirq-config = "ibase"; 107 intel,ibase-offset = <0x50>; 108 intel,actl-addr = <0>; 109 intel,pirq-link = <8 8>; 110 intel,pirq-mask = <0xdee0>; 111 intel,pirq-routing = < 112 /* BayTrail PCI devices */ 113 PCI_BDF(0, 2, 0) INTA PIRQA 114 PCI_BDF(0, 3, 0) INTA PIRQA 115 PCI_BDF(0, 16, 0) INTA PIRQA 116 PCI_BDF(0, 17, 0) INTA PIRQA 117 PCI_BDF(0, 18, 0) INTA PIRQA 118 PCI_BDF(0, 19, 0) INTA PIRQA 119 PCI_BDF(0, 20, 0) INTA PIRQA 120 PCI_BDF(0, 21, 0) INTA PIRQA 121 PCI_BDF(0, 22, 0) INTA PIRQA 122 PCI_BDF(0, 23, 0) INTA PIRQA 123 PCI_BDF(0, 24, 0) INTA PIRQA 124 PCI_BDF(0, 24, 1) INTC PIRQC 125 PCI_BDF(0, 24, 2) INTD PIRQD 126 PCI_BDF(0, 24, 3) INTB PIRQB 127 PCI_BDF(0, 24, 4) INTA PIRQA 128 PCI_BDF(0, 24, 5) INTC PIRQC 129 PCI_BDF(0, 24, 6) INTD PIRQD 130 PCI_BDF(0, 24, 7) INTB PIRQB 131 PCI_BDF(0, 26, 0) INTA PIRQA 132 PCI_BDF(0, 27, 0) INTA PIRQA 133 PCI_BDF(0, 28, 0) INTA PIRQA 134 PCI_BDF(0, 28, 1) INTB PIRQB 135 PCI_BDF(0, 28, 2) INTC PIRQC 136 PCI_BDF(0, 28, 3) INTD PIRQD 137 PCI_BDF(0, 29, 0) INTA PIRQA 138 PCI_BDF(0, 30, 0) INTA PIRQA 139 PCI_BDF(0, 30, 1) INTD PIRQD 140 PCI_BDF(0, 30, 2) INTB PIRQB 141 PCI_BDF(0, 30, 3) INTC PIRQC 142 PCI_BDF(0, 30, 4) INTD PIRQD 143 PCI_BDF(0, 30, 5) INTB PIRQB 144 PCI_BDF(0, 31, 3) INTB PIRQB 145 146 /* 147 * PCIe root ports downstream 148 * interrupts 149 */ 150 PCI_BDF(1, 0, 0) INTA PIRQA 151 PCI_BDF(1, 0, 0) INTB PIRQB 152 PCI_BDF(1, 0, 0) INTC PIRQC 153 PCI_BDF(1, 0, 0) INTD PIRQD 154 PCI_BDF(2, 0, 0) INTA PIRQB 155 PCI_BDF(2, 0, 0) INTB PIRQC 156 PCI_BDF(2, 0, 0) INTC PIRQD 157 PCI_BDF(2, 0, 0) INTD PIRQA 158 PCI_BDF(3, 0, 0) INTA PIRQC 159 PCI_BDF(3, 0, 0) INTB PIRQD 160 PCI_BDF(3, 0, 0) INTC PIRQA 161 PCI_BDF(3, 0, 0) INTD PIRQB 162 PCI_BDF(4, 0, 0) INTA PIRQD 163 PCI_BDF(4, 0, 0) INTB PIRQA 164 PCI_BDF(4, 0, 0) INTC PIRQB 165 PCI_BDF(4, 0, 0) INTD PIRQC 166 >; 167 }; 168 169 spi: spi { 170 #address-cells = <1>; 171 #size-cells = <0>; 172 compatible = "intel,ich9-spi"; 173 spi-flash@0 { 174 #address-cells = <1>; 175 #size-cells = <1>; 176 reg = <0>; 177 compatible = "winbond,w25q64dw", 178 "spi-flash"; 179 memory-map = <0xff800000 0x00800000>; 180 rw-mrc-cache { 181 label = "rw-mrc-cache"; 182 reg = <0x006e0000 0x00010000>; 183 }; 184 }; 185 }; 186 187 gpioa { 188 compatible = "intel,ich6-gpio"; 189 u-boot,dm-pre-reloc; 190 reg = <0 0x20>; 191 bank-name = "A"; 192 use-lvl-write-cache; 193 }; 194 195 gpiob { 196 compatible = "intel,ich6-gpio"; 197 u-boot,dm-pre-reloc; 198 reg = <0x20 0x20>; 199 bank-name = "B"; 200 use-lvl-write-cache; 201 }; 202 203 gpioc { 204 compatible = "intel,ich6-gpio"; 205 u-boot,dm-pre-reloc; 206 reg = <0x40 0x20>; 207 bank-name = "C"; 208 use-lvl-write-cache; 209 }; 210 211 gpiod { 212 compatible = "intel,ich6-gpio"; 213 u-boot,dm-pre-reloc; 214 reg = <0x60 0x20>; 215 bank-name = "D"; 216 use-lvl-write-cache; 217 }; 218 219 gpioe { 220 compatible = "intel,ich6-gpio"; 221 u-boot,dm-pre-reloc; 222 reg = <0x80 0x20>; 223 bank-name = "E"; 224 use-lvl-write-cache; 225 }; 226 227 gpiof { 228 compatible = "intel,ich6-gpio"; 229 u-boot,dm-pre-reloc; 230 reg = <0xA0 0x20>; 231 bank-name = "F"; 232 use-lvl-write-cache; 233 }; 234 }; 235 }; 236 237 fsp { 238 compatible = "intel,baytrail-fsp"; 239 fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>; 240 fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>; 241 fsp,mrc-init-spd-addr1 = <0xa0>; 242 fsp,mrc-init-spd-addr2 = <0xa2>; 243 fsp,emmc-boot-mode = <EMMC_BOOT_MODE_AUTO>; 244 fsp,enable-sdio; 245 fsp,enable-sdcard; 246 fsp,enable-hsuart1; 247 fsp,enable-spi; 248 fsp,enable-sata; 249 fsp,sata-mode = <SATA_MODE_AHCI>; 250 fsp,lpe-mode = <LPE_MODE_PCI>; 251 fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>; 252 fsp,enable-dma0; 253 fsp,enable-dma1; 254 fsp,enable-i2c0; 255 fsp,enable-i2c1; 256 fsp,enable-i2c2; 257 fsp,enable-i2c3; 258 fsp,enable-i2c4; 259 fsp,enable-i2c5; 260 fsp,enable-i2c6; 261 fsp,enable-pwm0; 262 fsp,enable-pwm1; 263 fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>; 264 fsp,aperture-size = <APERTURE_SIZE_256MB>; 265 fsp,gtt-size = <GTT_SIZE_2MB>; 266 fsp,scc-mode = <SCC_MODE_PCI>; 267 fsp,os-selection = <OS_SELECTION_LINUX>; 268 fsp,emmc45-ddr50-enabled; 269 fsp,emmc45-retune-timer-value = <8>; 270 fsp,enable-igd; 271 }; 272 273 microcode { 274 update@0 { 275#include "microcode/m0230671117.dtsi" 276 }; 277 update@1 { 278#include "microcode/m0130673325.dtsi" 279 }; 280 update@2 { 281#include "microcode/m0130679907.dtsi" 282 }; 283 }; 284 285}; 286