1 /* 2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <asm/irq.h> 10 #include <asm/pci.h> 11 #include <asm/post.h> 12 #include <asm/arch/device.h> 13 #include <asm/arch/tnc.h> 14 #include <asm/fsp/fsp_support.h> 15 #include <asm/processor.h> 16 17 static void unprotect_spi_flash(void) 18 { 19 u32 bc; 20 21 bc = x86_pci_read_config32(TNC_LPC, 0xd8); 22 bc |= 0x1; /* unprotect the flash */ 23 x86_pci_write_config32(TNC_LPC, 0xd8, bc); 24 } 25 26 int arch_cpu_init(void) 27 { 28 int ret; 29 30 post_code(POST_CPU_INIT); 31 #ifdef CONFIG_SYS_X86_TSC_TIMER 32 timer_set_base(rdtsc()); 33 #endif 34 35 ret = x86_cpu_init_f(); 36 if (ret) 37 return ret; 38 39 unprotect_spi_flash(); 40 41 return 0; 42 } 43 44 void cpu_irq_init(void) 45 { 46 struct tnc_rcba *rcba; 47 u32 base; 48 49 base = x86_pci_read_config32(TNC_LPC, LPC_RCBA); 50 base &= ~MEM_BAR_EN; 51 rcba = (struct tnc_rcba *)base; 52 53 /* Make sure all internal PCI devices are using INTA */ 54 writel(INTA, &rcba->d02ip); 55 writel(INTA, &rcba->d03ip); 56 writel(INTA, &rcba->d27ip); 57 writel(INTA, &rcba->d31ip); 58 writel(INTA, &rcba->d23ip); 59 writel(INTA, &rcba->d24ip); 60 writel(INTA, &rcba->d25ip); 61 writel(INTA, &rcba->d26ip); 62 63 /* 64 * Route TunnelCreek PCI device interrupt pin to PIRQ 65 * 66 * Since PCIe downstream ports received INTx are routed to PIRQ 67 * A/B/C/D directly and not configurable, we have to route PCIe 68 * root ports' INTx to PIRQ A/B/C/D as well. For other devices 69 * on TunneCreek, route them to PIRQ E/F/G/H. 70 */ 71 writew(PIRQE, &rcba->d02ir); 72 writew(PIRQF, &rcba->d03ir); 73 writew(PIRQG, &rcba->d27ir); 74 writew(PIRQH, &rcba->d31ir); 75 writew(PIRQA, &rcba->d23ir); 76 writew(PIRQB, &rcba->d24ir); 77 writew(PIRQC, &rcba->d25ir); 78 writew(PIRQD, &rcba->d26ir); 79 } 80 81 int arch_misc_init(void) 82 { 83 return pirq_init(); 84 } 85