1 /* 2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <asm/irq.h> 10 #include <asm/pci.h> 11 #include <asm/post.h> 12 #include <asm/arch/device.h> 13 #include <asm/arch/tnc.h> 14 #include <asm/fsp/fsp_support.h> 15 #include <asm/processor.h> 16 17 static void __maybe_unused disable_igd(void) 18 { 19 /* 20 * According to Atom E6xx datasheet, setting VGA Disable (bit17) 21 * of Graphics Controller register (offset 0x50) prevents IGD 22 * (D2:F0) from reporting itself as a VGA display controller 23 * class in the PCI configuration space, and should also prevent 24 * it from responding to VGA legacy memory range and I/O addresses. 25 * 26 * However test result shows that with just VGA Disable bit set and 27 * a PCIe graphics card connected to one of the PCIe controllers on 28 * the E6xx, accessing the VGA legacy space still causes system hang. 29 * After a number of attempts, it turns out besides VGA Disable bit, 30 * the SDVO (D3:F0) device should be disabled to make it work. 31 * 32 * To simplify, use the Function Disable register (offset 0xc4) 33 * to disable both IGD (D2:F0) and SDVO (D3:F0) devices. Now these 34 * two devices will be completely disabled (invisible in the PCI 35 * configuration space) unless a system reset is performed. 36 */ 37 x86_pci_write_config32(TNC_IGD, IGD_FD, FUNC_DISABLE); 38 x86_pci_write_config32(TNC_SDVO, IGD_FD, FUNC_DISABLE); 39 } 40 41 int arch_cpu_init(void) 42 { 43 int ret; 44 45 post_code(POST_CPU_INIT); 46 47 ret = x86_cpu_init_f(); 48 if (ret) 49 return ret; 50 51 return 0; 52 } 53 54 int arch_early_init_r(void) 55 { 56 #ifdef CONFIG_DISABLE_IGD 57 disable_igd(); 58 #endif 59 60 return 0; 61 } 62