1 /* 2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <asm/irq.h> 10 #include <asm/pci.h> 11 #include <asm/post.h> 12 #include <asm/arch/device.h> 13 #include <asm/arch/tnc.h> 14 #include <asm/fsp/fsp_support.h> 15 #include <asm/processor.h> 16 17 static void unprotect_spi_flash(void) 18 { 19 u32 bc; 20 21 bc = x86_pci_read_config32(TNC_LPC, 0xd8); 22 bc |= 0x1; /* unprotect the flash */ 23 x86_pci_write_config32(TNC_LPC, 0xd8, bc); 24 } 25 26 static void __maybe_unused disable_igd(void) 27 { 28 /* 29 * According to Atom E6xx datasheet, setting VGA Disable (bit17) 30 * of Graphics Controller register (offset 0x50) prevents IGD 31 * (D2:F0) from reporting itself as a VGA display controller 32 * class in the PCI configuration space, and should also prevent 33 * it from responding to VGA legacy memory range and I/O addresses. 34 * 35 * However test result shows that with just VGA Disable bit set and 36 * a PCIe graphics card connected to one of the PCIe controllers on 37 * the E6xx, accessing the VGA legacy space still causes system hang. 38 * After a number of attempts, it turns out besides VGA Disable bit, 39 * the SDVO (D3:F0) device should be disabled to make it work. 40 * 41 * To simplify, use the Function Disable register (offset 0xc4) 42 * to disable both IGD (D2:F0) and SDVO (D3:F0) devices. Now these 43 * two devices will be completely disabled (invisible in the PCI 44 * configuration space) unless a system reset is performed. 45 */ 46 x86_pci_write_config32(TNC_IGD, IGD_FD, FUNC_DISABLE); 47 x86_pci_write_config32(TNC_SDVO, IGD_FD, FUNC_DISABLE); 48 } 49 50 int arch_cpu_init(void) 51 { 52 int ret; 53 54 post_code(POST_CPU_INIT); 55 #ifdef CONFIG_SYS_X86_TSC_TIMER 56 timer_set_base(rdtsc()); 57 #endif 58 59 ret = x86_cpu_init_f(); 60 if (ret) 61 return ret; 62 63 return 0; 64 } 65 66 int arch_early_init_r(void) 67 { 68 #ifdef CONFIG_DISABLE_IGD 69 disable_igd(); 70 #endif 71 72 return 0; 73 } 74 75 void cpu_irq_init(void) 76 { 77 struct tnc_rcba *rcba; 78 u32 base; 79 80 base = x86_pci_read_config32(TNC_LPC, LPC_RCBA); 81 base &= ~MEM_BAR_EN; 82 rcba = (struct tnc_rcba *)base; 83 84 /* Make sure all internal PCI devices are using INTA */ 85 writel(INTA, &rcba->d02ip); 86 writel(INTA, &rcba->d03ip); 87 writel(INTA, &rcba->d27ip); 88 writel(INTA, &rcba->d31ip); 89 writel(INTA, &rcba->d23ip); 90 writel(INTA, &rcba->d24ip); 91 writel(INTA, &rcba->d25ip); 92 writel(INTA, &rcba->d26ip); 93 94 /* 95 * Route TunnelCreek PCI device interrupt pin to PIRQ 96 * 97 * Since PCIe downstream ports received INTx are routed to PIRQ 98 * A/B/C/D directly and not configurable, we have to route PCIe 99 * root ports' INTx to PIRQ A/B/C/D as well. For other devices 100 * on TunneCreek, route them to PIRQ E/F/G/H. 101 */ 102 writew(PIRQE, &rcba->d02ir); 103 writew(PIRQF, &rcba->d03ir); 104 writew(PIRQG, &rcba->d27ir); 105 writew(PIRQH, &rcba->d31ir); 106 writew(PIRQA, &rcba->d23ir); 107 writew(PIRQB, &rcba->d24ir); 108 writew(PIRQC, &rcba->d25ir); 109 writew(PIRQD, &rcba->d26ir); 110 } 111 112 int arch_misc_init(void) 113 { 114 unprotect_spi_flash(); 115 116 return pirq_init(); 117 } 118