xref: /openbmc/u-boot/arch/x86/cpu/queensbay/Kconfig (revision a3b36c84)
1#
2# Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
3#
4# SPDX-License-Identifier:	GPL-2.0+
5#
6
7config INTEL_QUEENSBAY
8	bool
9	select HAVE_FSP
10	select HAVE_CMC
11	select ARCH_EARLY_INIT_R
12	imply AHCI_PCI
13	imply ICH_SPI
14	imply INTEL_ICH6_GPIO
15	imply MMC
16	imply MMC_PCI
17	imply MMC_SDHCI
18	imply MMC_SDHCI_SDMA
19	imply PCH_GBE
20	imply SCSI
21	imply SPI_FLASH
22	imply SYS_NS16550
23	imply USB
24	imply USB_EHCI_HCD
25	imply VIDEO_VESA
26
27if INTEL_QUEENSBAY
28
29config HAVE_CMC
30	bool "Add a Chipset Micro Code state machine binary"
31	help
32	  Select this option to add a Chipset Micro Code state machine binary
33	  to the resulting U-Boot image. It is a 64K data block of machine
34	  specific code which must be put in the flash for the processor to
35	  access when powered up before system BIOS is executed.
36
37config CMC_FILE
38	string "Chipset Micro Code state machine filename"
39	depends on HAVE_CMC
40	default "cmc.bin"
41	help
42	  The filename of the file to use as Chipset Micro Code state machine
43	  binary in the board directory.
44
45config CMC_ADDR
46	hex "Chipset Micro Code state machine binary location"
47	depends on HAVE_CMC
48	default 0xfffb0000
49	help
50	  The location of the CMC binary is determined by a strap. It must be
51	  put in flash at a location matching the strap-determined base address.
52
53	  The default base address of 0xfffb0000 indicates that the binary must
54	  be located at offset 0xb0000 from the beginning of a 1MB flash device.
55
56config CPU_ADDR_BITS
57	int
58	default 32
59
60config DISABLE_IGD
61	bool "Disable Integrated Graphics Device (IGD)"
62	help
63	  Disable the Integrated Graphics Device (IGD) so that it does not
64	  show in the PCI configuration space as a VGA disaplay controller.
65	  This gives a chance for U-Boot to run PCI/PCIe based graphics
66	  card's VGA BIOS and use that card for the graphics console.
67
68endif
69