1 /* 2 * Copyright (C) 2013, Intel Corporation 3 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 4 * 5 * Ported from Intel released Quark UEFI BIOS 6 * QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei 7 * 8 * SPDX-License-Identifier: Intel 9 */ 10 11 #ifndef _SMC_H_ 12 #define _SMC_H_ 13 14 /* System Memory Controller Register Defines */ 15 16 /* Memory Controller Message Bus Registers Offsets */ 17 #define DRP 0x00 18 #define DTR0 0x01 19 #define DTR1 0x02 20 #define DTR2 0x03 21 #define DTR3 0x04 22 #define DTR4 0x05 23 #define DPMC0 0x06 24 #define DPMC1 0x07 25 #define DRFC 0x08 26 #define DSCH 0x09 27 #define DCAL 0x0a 28 #define DRMC 0x0b 29 #define PMSTS 0x0c 30 #define DCO 0x0f 31 #define DSTAT 0x20 32 #define SSKPD0 0x4a 33 #define SSKPD1 0x4b 34 #define DECCCTRL 0x60 35 #define DECCSTAT 0x61 36 #define DECCSBECNT 0x62 37 #define DECCSBECA 0x68 38 #define DECCSBECS 0x69 39 #define DECCDBECA 0x6a 40 #define DECCDBECS 0x6b 41 #define DFUSESTAT 0x70 42 #define SCRMSEED 0x80 43 #define SCRMLO 0x81 44 #define SCRMHI 0x82 45 46 /* DRP register defines */ 47 #define DRP_RKEN0 (1 << 0) 48 #define DRP_RKEN1 (1 << 1) 49 #define DRP_PRI64BSPLITEN (1 << 13) 50 #define DRP_ADDRMAP_MAP0 (1 << 14) 51 #define DRP_ADDRMAP_MAP1 (1 << 15) 52 #define DRP_ADDRMAP_MASK 0x0000c000 53 54 /* DTR0 register defines */ 55 #define DTR0_DFREQ_MASK 0x00000003 56 #define DTR0_TRP_MASK 0x000000f0 57 #define DTR0_TRCD_MASK 0x00000f00 58 #define DTR0_TCL_MASK 0x00007000 59 60 /* DTR1 register defines */ 61 #define DTR1_TWCL_MASK 0x00000007 62 #define DTR1_TCMD_MASK 0x00000030 63 #define DTR1_TWTP_MASK 0x00000f00 64 #define DTR1_TCCD_12CLK (1 << 12) 65 #define DTR1_TCCD_18CLK (1 << 13) 66 #define DTR1_TCCD_MASK 0x00003000 67 #define DTR1_TFAW_MASK 0x000f0000 68 #define DTR1_TRAS_MASK 0x00f00000 69 #define DTR1_TRRD_MASK 0x03000000 70 #define DTR1_TRTP_MASK 0x70000000 71 72 /* DTR2 register defines */ 73 #define DTR2_TRRDR_MASK 0x00000007 74 #define DTR2_TWWDR_MASK 0x00000700 75 #define DTR2_TRWDR_MASK 0x000f0000 76 77 /* DTR3 register defines */ 78 #define DTR3_TWRDR_MASK 0x00000007 79 #define DTR3_TXXXX_MASK 0x00000070 80 #define DTR3_TRWSR_MASK 0x00000f00 81 #define DTR3_TWRSR_MASK 0x0001e000 82 #define DTR3_TXP_MASK 0x00c00000 83 84 /* DTR4 register defines */ 85 #define DTR4_WRODTSTRT_MASK 0x00000003 86 #define DTR4_WRODTSTOP_MASK 0x00000070 87 #define DTR4_XXXX1_MASK 0x00000700 88 #define DTR4_XXXX2_MASK 0x00007000 89 #define DTR4_ODTDIS (1 << 15) 90 #define DTR4_TRGSTRDIS (1 << 16) 91 92 /* DPMC0 register defines */ 93 #define DPMC0_PCLSTO_MASK 0x00070000 94 #define DPMC0_PREAPWDEN (1 << 21) 95 #define DPMC0_DYNSREN (1 << 23) 96 #define DPMC0_CLKGTDIS (1 << 24) 97 #define DPMC0_DISPWRDN (1 << 25) 98 #define DPMC0_ENPHYCLKGATE (1 << 29) 99 100 /* DRFC register defines */ 101 #define DRFC_TREFI_MASK 0x00007000 102 #define DRFC_REFDBTCLR (1 << 21) 103 104 /* DSCH register defines */ 105 #define DSCH_OOODIS (1 << 8) 106 #define DSCH_OOOST3DIS (1 << 9) 107 #define DSCH_NEWBYPDIS (1 << 12) 108 109 /* DCAL register defines */ 110 #define DCAL_ZQCINT_MASK 0x00000700 111 #define DCAL_SRXZQCL_MASK 0x00003000 112 113 /* DRMC register defines */ 114 #define DRMC_CKEMODE (1 << 4) 115 #define DRMC_ODTMODE (1 << 12) 116 #define DRMC_COLDWAKE (1 << 16) 117 118 /* PMSTS register defines */ 119 #define PMSTS_DISR (1 << 0) 120 121 /* DCO register defines */ 122 #define DCO_DRPLOCK (1 << 0) 123 #define DCO_CPGCLOCK (1 << 8) 124 #define DCO_PMICTL (1 << 28) 125 #define DCO_PMIDIS (1 << 29) 126 #define DCO_IC (1 << 31) 127 128 /* DECCCTRL register defines */ 129 #define DECCCTRL_SBEEN (1 << 0) 130 #define DECCCTRL_DBEEN (1 << 1) 131 #define DECCCTRL_ENCBGEN (1 << 17) 132 133 /* DRAM init command */ 134 #define DCMD_MRS1(rnk, dat) (0 | ((rnk) << 22) | (1 << 3) | ((dat) << 6)) 135 #define DCMD_REF(rnk) (1 | ((rnk) << 22)) 136 #define DCMD_PRE(rnk) (2 | ((rnk) << 22)) 137 #define DCMD_PREA(rnk) (2 | ((rnk) << 22) | (0x400 << 6)) 138 #define DCMD_ACT(rnk, row) (3 | ((rnk) << 22) | ((row) << 6)) 139 #define DCMD_WR(rnk, col) (4 | ((rnk) << 22) | ((col) << 6)) 140 #define DCMD_RD(rnk, col) (5 | ((rnk) << 22) | ((col) << 6)) 141 #define DCMD_ZQCS(rnk) (6 | ((rnk) << 22)) 142 #define DCMD_ZQCL(rnk) (6 | ((rnk) << 22) | (0x400 << 6)) 143 #define DCMD_NOP(rnk) (7 | ((rnk) << 22)) 144 145 #define DDR3_EMRS1_DIC_40 0 146 #define DDR3_EMRS1_DIC_34 1 147 148 #define DDR3_EMRS1_RTTNOM_0 0 149 #define DDR3_EMRS1_RTTNOM_60 0x04 150 #define DDR3_EMRS1_RTTNOM_120 0x40 151 #define DDR3_EMRS1_RTTNOM_40 0x44 152 #define DDR3_EMRS1_RTTNOM_20 0x200 153 #define DDR3_EMRS1_RTTNOM_30 0x204 154 155 #define DDR3_EMRS2_RTTWR_60 (1 << 9) 156 #define DDR3_EMRS2_RTTWR_120 (1 << 10) 157 158 /* BEGIN DDRIO Registers */ 159 160 /* DDR IOs & COMPs */ 161 #define DDRIODQ_BL_OFFSET 0x0800 162 #define DDRIODQ_CH_OFFSET ((NUM_BYTE_LANES / 2) * DDRIODQ_BL_OFFSET) 163 #define DDRIOCCC_CH_OFFSET 0x0800 164 #define DDRCOMP_CH_OFFSET 0x0100 165 166 /* CH0-BL01-DQ */ 167 #define DQOBSCKEBBCTL 0x0000 168 #define DQDLLTXCTL 0x0004 169 #define DQDLLRXCTL 0x0008 170 #define DQMDLLCTL 0x000c 171 #define B0RXIOBUFCTL 0x0010 172 #define B0VREFCTL 0x0014 173 #define B0RXOFFSET1 0x0018 174 #define B0RXOFFSET0 0x001c 175 #define B1RXIOBUFCTL 0x0020 176 #define B1VREFCTL 0x0024 177 #define B1RXOFFSET1 0x0028 178 #define B1RXOFFSET0 0x002c 179 #define DQDFTCTL 0x0030 180 #define DQTRAINSTS 0x0034 181 #define B1DLLPICODER0 0x0038 182 #define B0DLLPICODER0 0x003c 183 #define B1DLLPICODER1 0x0040 184 #define B0DLLPICODER1 0x0044 185 #define B1DLLPICODER2 0x0048 186 #define B0DLLPICODER2 0x004c 187 #define B1DLLPICODER3 0x0050 188 #define B0DLLPICODER3 0x0054 189 #define B1RXDQSPICODE 0x0058 190 #define B0RXDQSPICODE 0x005c 191 #define B1RXDQPICODER32 0x0060 192 #define B1RXDQPICODER10 0x0064 193 #define B0RXDQPICODER32 0x0068 194 #define B0RXDQPICODER10 0x006c 195 #define B01PTRCTL0 0x0070 196 #define B01PTRCTL1 0x0074 197 #define B01DBCTL0 0x0078 198 #define B01DBCTL1 0x007c 199 #define B0LATCTL0 0x0080 200 #define B1LATCTL0 0x0084 201 #define B01LATCTL1 0x0088 202 #define B0ONDURCTL 0x008c 203 #define B1ONDURCTL 0x0090 204 #define B0OVRCTL 0x0094 205 #define B1OVRCTL 0x0098 206 #define DQCTL 0x009c 207 #define B0RK2RKCHGPTRCTRL 0x00a0 208 #define B1RK2RKCHGPTRCTRL 0x00a4 209 #define DQRK2RKCTL 0x00a8 210 #define DQRK2RKPTRCTL 0x00ac 211 #define B0RK2RKLAT 0x00b0 212 #define B1RK2RKLAT 0x00b4 213 #define DQCLKALIGNREG0 0x00b8 214 #define DQCLKALIGNREG1 0x00bc 215 #define DQCLKALIGNREG2 0x00c0 216 #define DQCLKALIGNSTS0 0x00c4 217 #define DQCLKALIGNSTS1 0x00c8 218 #define DQCLKGATE 0x00cc 219 #define B0COMPSLV1 0x00d0 220 #define B1COMPSLV1 0x00d4 221 #define B0COMPSLV2 0x00d8 222 #define B1COMPSLV2 0x00dc 223 #define B0COMPSLV3 0x00e0 224 #define B1COMPSLV3 0x00e4 225 #define DQVISALANECR0TOP 0x00e8 226 #define DQVISALANECR1TOP 0x00ec 227 #define DQVISACONTROLCRTOP 0x00f0 228 #define DQVISALANECR0BL 0x00f4 229 #define DQVISALANECR1BL 0x00f8 230 #define DQVISACONTROLCRBL 0x00fc 231 #define DQTIMINGCTRL 0x010c 232 233 /* CH0-ECC */ 234 #define ECCDLLTXCTL 0x2004 235 #define ECCDLLRXCTL 0x2008 236 #define ECCMDLLCTL 0x200c 237 #define ECCB1DLLPICODER0 0x2038 238 #define ECCB1DLLPICODER1 0x2040 239 #define ECCB1DLLPICODER2 0x2048 240 #define ECCB1DLLPICODER3 0x2050 241 #define ECCB01DBCTL0 0x2078 242 #define ECCB01DBCTL1 0x207c 243 #define ECCCLKALIGNREG0 0x20b8 244 #define ECCCLKALIGNREG1 0x20bc 245 #define ECCCLKALIGNREG2 0x20c0 246 247 /* CH0-CMD */ 248 #define CMDOBSCKEBBCTL 0x4800 249 #define CMDDLLTXCTL 0x4808 250 #define CMDDLLRXCTL 0x480c 251 #define CMDMDLLCTL 0x4810 252 #define CMDRCOMPODT 0x4814 253 #define CMDDLLPICODER0 0x4820 254 #define CMDDLLPICODER1 0x4824 255 #define CMDCFGREG0 0x4840 256 #define CMDPTRREG 0x4844 257 #define CMDCLKALIGNREG0 0x4850 258 #define CMDCLKALIGNREG1 0x4854 259 #define CMDCLKALIGNREG2 0x4858 260 #define CMDPMCONFIG0 0x485c 261 #define CMDPMDLYREG0 0x4860 262 #define CMDPMDLYREG1 0x4864 263 #define CMDPMDLYREG2 0x4868 264 #define CMDPMDLYREG3 0x486c 265 #define CMDPMDLYREG4 0x4870 266 #define CMDCLKALIGNSTS0 0x4874 267 #define CMDCLKALIGNSTS1 0x4878 268 #define CMDPMSTS0 0x487c 269 #define CMDPMSTS1 0x4880 270 #define CMDCOMPSLV 0x4884 271 #define CMDBONUS0 0x488c 272 #define CMDBONUS1 0x4890 273 #define CMDVISALANECR0 0x4894 274 #define CMDVISALANECR1 0x4898 275 #define CMDVISACONTROLCR 0x489c 276 #define CMDCLKGATE 0x48a0 277 #define CMDTIMINGCTRL 0x48a4 278 279 /* CH0-CLK-CTL */ 280 #define CCOBSCKEBBCTL 0x5800 281 #define CCRCOMPIO 0x5804 282 #define CCDLLTXCTL 0x5808 283 #define CCDLLRXCTL 0x580c 284 #define CCMDLLCTL 0x5810 285 #define CCRCOMPODT 0x5814 286 #define CCDLLPICODER0 0x5820 287 #define CCDLLPICODER1 0x5824 288 #define CCDDR3RESETCTL 0x5830 289 #define CCCFGREG0 0x5838 290 #define CCCFGREG1 0x5840 291 #define CCPTRREG 0x5844 292 #define CCCLKALIGNREG0 0x5850 293 #define CCCLKALIGNREG1 0x5854 294 #define CCCLKALIGNREG2 0x5858 295 #define CCPMCONFIG0 0x585c 296 #define CCPMDLYREG0 0x5860 297 #define CCPMDLYREG1 0x5864 298 #define CCPMDLYREG2 0x5868 299 #define CCPMDLYREG3 0x586c 300 #define CCPMDLYREG4 0x5870 301 #define CCCLKALIGNSTS0 0x5874 302 #define CCCLKALIGNSTS1 0x5878 303 #define CCPMSTS0 0x587c 304 #define CCPMSTS1 0x5880 305 #define CCCOMPSLV1 0x5884 306 #define CCCOMPSLV2 0x5888 307 #define CCCOMPSLV3 0x588c 308 #define CCBONUS0 0x5894 309 #define CCBONUS1 0x5898 310 #define CCVISALANECR0 0x589c 311 #define CCVISALANECR1 0x58a0 312 #define CCVISACONTROLCR 0x58a4 313 #define CCCLKGATE 0x58a8 314 #define CCTIMINGCTL 0x58ac 315 316 /* COMP */ 317 #define CMPCTRL 0x6800 318 #define SOFTRSTCNTL 0x6804 319 #define MSCNTR 0x6808 320 #define NMSCNTRL 0x680c 321 #define LATCH1CTL 0x6814 322 #define COMPVISALANECR0 0x681c 323 #define COMPVISALANECR1 0x6820 324 #define COMPVISACONTROLCR 0x6824 325 #define COMPBONUS0 0x6830 326 #define TCOCNTCTRL 0x683c 327 #define DQANAODTPUCTL 0x6840 328 #define DQANAODTPDCTL 0x6844 329 #define DQANADRVPUCTL 0x6848 330 #define DQANADRVPDCTL 0x684c 331 #define DQANADLYPUCTL 0x6850 332 #define DQANADLYPDCTL 0x6854 333 #define DQANATCOPUCTL 0x6858 334 #define DQANATCOPDCTL 0x685c 335 #define CMDANADRVPUCTL 0x6868 336 #define CMDANADRVPDCTL 0x686c 337 #define CMDANADLYPUCTL 0x6870 338 #define CMDANADLYPDCTL 0x6874 339 #define CLKANAODTPUCTL 0x6880 340 #define CLKANAODTPDCTL 0x6884 341 #define CLKANADRVPUCTL 0x6888 342 #define CLKANADRVPDCTL 0x688c 343 #define CLKANADLYPUCTL 0x6890 344 #define CLKANADLYPDCTL 0x6894 345 #define CLKANATCOPUCTL 0x6898 346 #define CLKANATCOPDCTL 0x689c 347 #define DQSANAODTPUCTL 0x68a0 348 #define DQSANAODTPDCTL 0x68a4 349 #define DQSANADRVPUCTL 0x68a8 350 #define DQSANADRVPDCTL 0x68ac 351 #define DQSANADLYPUCTL 0x68b0 352 #define DQSANADLYPDCTL 0x68b4 353 #define DQSANATCOPUCTL 0x68b8 354 #define DQSANATCOPDCTL 0x68bc 355 #define CTLANADRVPUCTL 0x68c8 356 #define CTLANADRVPDCTL 0x68cc 357 #define CTLANADLYPUCTL 0x68d0 358 #define CTLANADLYPDCTL 0x68d4 359 #define CHNLBUFSTATIC 0x68f0 360 #define COMPOBSCNTRL 0x68f4 361 #define COMPBUFFDBG0 0x68f8 362 #define COMPBUFFDBG1 0x68fc 363 #define CFGMISCCH0 0x6900 364 #define COMPEN0CH0 0x6904 365 #define COMPEN1CH0 0x6908 366 #define COMPEN2CH0 0x690c 367 #define STATLEGEN0CH0 0x6910 368 #define STATLEGEN1CH0 0x6914 369 #define DQVREFCH0 0x6918 370 #define CMDVREFCH0 0x691c 371 #define CLKVREFCH0 0x6920 372 #define DQSVREFCH0 0x6924 373 #define CTLVREFCH0 0x6928 374 #define TCOVREFCH0 0x692c 375 #define DLYSELCH0 0x6930 376 #define TCODRAMBUFODTCH0 0x6934 377 #define CCBUFODTCH0 0x6938 378 #define RXOFFSETCH0 0x693c 379 #define DQODTPUCTLCH0 0x6940 380 #define DQODTPDCTLCH0 0x6944 381 #define DQDRVPUCTLCH0 0x6948 382 #define DQDRVPDCTLCH0 0x694c 383 #define DQDLYPUCTLCH0 0x6950 384 #define DQDLYPDCTLCH0 0x6954 385 #define DQTCOPUCTLCH0 0x6958 386 #define DQTCOPDCTLCH0 0x695c 387 #define CMDDRVPUCTLCH0 0x6968 388 #define CMDDRVPDCTLCH0 0x696c 389 #define CMDDLYPUCTLCH0 0x6970 390 #define CMDDLYPDCTLCH0 0x6974 391 #define CLKODTPUCTLCH0 0x6980 392 #define CLKODTPDCTLCH0 0x6984 393 #define CLKDRVPUCTLCH0 0x6988 394 #define CLKDRVPDCTLCH0 0x698c 395 #define CLKDLYPUCTLCH0 0x6990 396 #define CLKDLYPDCTLCH0 0x6994 397 #define CLKTCOPUCTLCH0 0x6998 398 #define CLKTCOPDCTLCH0 0x699c 399 #define DQSODTPUCTLCH0 0x69a0 400 #define DQSODTPDCTLCH0 0x69a4 401 #define DQSDRVPUCTLCH0 0x69a8 402 #define DQSDRVPDCTLCH0 0x69ac 403 #define DQSDLYPUCTLCH0 0x69b0 404 #define DQSDLYPDCTLCH0 0x69b4 405 #define DQSTCOPUCTLCH0 0x69b8 406 #define DQSTCOPDCTLCH0 0x69bc 407 #define CTLDRVPUCTLCH0 0x69c8 408 #define CTLDRVPDCTLCH0 0x69cc 409 #define CTLDLYPUCTLCH0 0x69d0 410 #define CTLDLYPDCTLCH0 0x69d4 411 #define FNLUPDTCTLCH0 0x69f0 412 413 /* PLL */ 414 #define MPLLCTRL0 0x7800 415 #define MPLLCTRL1 0x7808 416 #define MPLLCSR0 0x7810 417 #define MPLLCSR1 0x7814 418 #define MPLLCSR2 0x7820 419 #define MPLLDFT 0x7828 420 #define MPLLMON0CTL 0x7830 421 #define MPLLMON1CTL 0x7838 422 #define MPLLMON2CTL 0x783c 423 #define SFRTRIM 0x7850 424 #define MPLLDFTOUT0 0x7858 425 #define MPLLDFTOUT1 0x785c 426 #define MASTERRSTN 0x7880 427 #define PLLLOCKDEL 0x7884 428 #define SFRDEL 0x7888 429 #define CRUVISALANECR0 0x78f0 430 #define CRUVISALANECR1 0x78f4 431 #define CRUVISACONTROLCR 0x78f8 432 #define IOSFVISALANECR0 0x78fc 433 #define IOSFVISALANECR1 0x7900 434 #define IOSFVISACONTROLCR 0x7904 435 436 /* END DDRIO Registers */ 437 438 /* DRAM Specific Message Bus OpCodes */ 439 #define MSG_OP_DRAM_INIT 0x68 440 #define MSG_OP_DRAM_WAKE 0xca 441 442 #define SAMPLE_SIZE 6 443 444 /* must be less than this number to enable early deadband */ 445 #define EARLY_DB 0x12 446 /* must be greater than this number to enable late deadband */ 447 #define LATE_DB 0x34 448 449 #define CHX_REGS (11 * 4) 450 #define FULL_CLK 128 451 #define HALF_CLK 64 452 #define QRTR_CLK 32 453 454 #define MCEIL(num, den) ((uint8_t)((num + den - 1) / den)) 455 #define MMAX(a, b) ((a) > (b) ? (a) : (b)) 456 #define DEAD_LOOP() for (;;); 457 458 #define MIN_RDQS_EYE 10 /* in PI Codes */ 459 #define MIN_VREF_EYE 10 /* in VREF Codes */ 460 /* how many RDQS codes to jump while margining */ 461 #define RDQS_STEP 1 462 /* how many VREF codes to jump while margining */ 463 #define VREF_STEP 1 464 /* offset into "vref_codes[]" for minimum allowed VREF setting */ 465 #define VREF_MIN 0x00 466 /* offset into "vref_codes[]" for maximum allowed VREF setting */ 467 #define VREF_MAX 0x3f 468 #define RDQS_MIN 0x00 /* minimum RDQS delay value */ 469 #define RDQS_MAX 0x3f /* maximum RDQS delay value */ 470 471 /* how many WDQ codes to jump while margining */ 472 #define WDQ_STEP 1 473 474 enum { 475 B, /* BOTTOM VREF */ 476 T /* TOP VREF */ 477 }; 478 479 enum { 480 L, /* LEFT RDQS */ 481 R /* RIGHT RDQS */ 482 }; 483 484 /* Memory Options */ 485 486 /* enable STATIC timing settings for RCVN (BACKUP_MODE) */ 487 #undef BACKUP_RCVN 488 /* enable STATIC timing settings for WDQS (BACKUP_MODE) */ 489 #undef BACKUP_WDQS 490 /* enable STATIC timing settings for RDQS (BACKUP_MODE) */ 491 #undef BACKUP_RDQS 492 /* enable STATIC timing settings for WDQ (BACKUP_MODE) */ 493 #undef BACKUP_WDQ 494 /* enable *COMP overrides (BACKUP_MODE) */ 495 #undef BACKUP_COMPS 496 /* enable the RD_TRAIN eye check */ 497 #undef RX_EYE_CHECK 498 499 /* enable Host to Memory Clock Alignment */ 500 #define HMC_TEST 501 /* enable multi-rank support via rank2rank sharing */ 502 #define R2R_SHARING 503 /* disable signals not used in 16bit mode of DDRIO */ 504 #define FORCE_16BIT_DDRIO 505 506 #define PLATFORM_ID 1 507 508 void clear_self_refresh(struct mrc_params *mrc_params); 509 void prog_ddr_timing_control(struct mrc_params *mrc_params); 510 void prog_decode_before_jedec(struct mrc_params *mrc_params); 511 void perform_ddr_reset(struct mrc_params *mrc_params); 512 void ddrphy_init(struct mrc_params *mrc_params); 513 void perform_jedec_init(struct mrc_params *mrc_params); 514 void set_ddr_init_complete(struct mrc_params *mrc_params); 515 void restore_timings(struct mrc_params *mrc_params); 516 void default_timings(struct mrc_params *mrc_params); 517 void rcvn_cal(struct mrc_params *mrc_params); 518 void wr_level(struct mrc_params *mrc_params); 519 void prog_page_ctrl(struct mrc_params *mrc_params); 520 void rd_train(struct mrc_params *mrc_params); 521 void wr_train(struct mrc_params *mrc_params); 522 void store_timings(struct mrc_params *mrc_params); 523 void enable_scrambling(struct mrc_params *mrc_params); 524 void prog_ddr_control(struct mrc_params *mrc_params); 525 void prog_dra_drb(struct mrc_params *mrc_params); 526 void perform_wake(struct mrc_params *mrc_params); 527 void change_refresh_period(struct mrc_params *mrc_params); 528 void set_auto_refresh(struct mrc_params *mrc_params); 529 void ecc_enable(struct mrc_params *mrc_params); 530 void memory_test(struct mrc_params *mrc_params); 531 void lock_registers(struct mrc_params *mrc_params); 532 533 #endif /* _SMC_H_ */ 534