1 /* 2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <mmc.h> 9 #include <asm/io.h> 10 #include <asm/irq.h> 11 #include <asm/mrccache.h> 12 #include <asm/mtrr.h> 13 #include <asm/pci.h> 14 #include <asm/post.h> 15 #include <asm/processor.h> 16 #include <asm/arch/device.h> 17 #include <asm/arch/msg_port.h> 18 #include <asm/arch/quark.h> 19 20 static struct pci_device_id mmc_supported[] = { 21 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_SDIO }, 22 }; 23 24 /* 25 * TODO: 26 * 27 * This whole routine should be removed until we fully convert the ICH SPI 28 * driver to DM and make use of DT to pass the bios control register offset 29 */ 30 static void unprotect_spi_flash(void) 31 { 32 u32 bc; 33 34 qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, 0xd8, &bc); 35 bc |= 0x1; /* unprotect the flash */ 36 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, 0xd8, bc); 37 } 38 39 static void quark_setup_mtrr(void) 40 { 41 u32 base, mask; 42 int i; 43 44 disable_caches(); 45 46 /* mark the VGA RAM area as uncacheable */ 47 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_A0000, 48 MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE)); 49 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_B0000, 50 MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE)); 51 52 /* mark other fixed range areas as cacheable */ 53 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_64K_00000, 54 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); 55 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_64K_40000, 56 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); 57 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_80000, 58 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); 59 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_90000, 60 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); 61 for (i = MTRR_FIX_4K_C0000; i <= MTRR_FIX_4K_FC000; i++) 62 msg_port_write(MSG_PORT_HOST_BRIDGE, i, 63 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); 64 65 /* variable range MTRR#0: ROM area */ 66 mask = ~(CONFIG_SYS_MONITOR_LEN - 1); 67 base = CONFIG_SYS_TEXT_BASE & mask; 68 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_ROM), 69 base | MTRR_TYPE_WRBACK); 70 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_ROM), 71 mask | MTRR_PHYS_MASK_VALID); 72 73 /* variable range MTRR#1: eSRAM area */ 74 mask = ~(ESRAM_SIZE - 1); 75 base = CONFIG_ESRAM_BASE & mask; 76 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_ESRAM), 77 base | MTRR_TYPE_WRBACK); 78 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_ESRAM), 79 mask | MTRR_PHYS_MASK_VALID); 80 81 /* enable both variable and fixed range MTRRs */ 82 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_DEF_TYPE, 83 MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN); 84 85 enable_caches(); 86 } 87 88 static void quark_setup_bars(void) 89 { 90 /* GPIO - D31:F0:R44h */ 91 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA, 92 CONFIG_GPIO_BASE | IO_BAR_EN); 93 94 /* ACPI PM1 Block - D31:F0:R48h */ 95 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_PM1BLK, 96 CONFIG_ACPI_PM1_BASE | IO_BAR_EN); 97 98 /* GPE0 - D31:F0:R4Ch */ 99 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GPE0BLK, 100 CONFIG_ACPI_GPE0_BASE | IO_BAR_EN); 101 102 /* WDT - D31:F0:R84h */ 103 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_WDTBA, 104 CONFIG_WDT_BASE | IO_BAR_EN); 105 106 /* RCBA - D31:F0:RF0h */ 107 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, 108 CONFIG_RCBA_BASE | MEM_BAR_EN); 109 110 /* ACPI P Block - Msg Port 04:R70h */ 111 msg_port_write(MSG_PORT_RMU, PBLK_BA, 112 CONFIG_ACPI_PBLK_BASE | IO_BAR_EN); 113 114 /* SPI DMA - Msg Port 04:R7Ah */ 115 msg_port_write(MSG_PORT_RMU, SPI_DMA_BA, 116 CONFIG_SPI_DMA_BASE | IO_BAR_EN); 117 118 /* PCIe ECAM */ 119 msg_port_write(MSG_PORT_MEM_ARBITER, AEC_CTRL, 120 CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN); 121 msg_port_write(MSG_PORT_HOST_BRIDGE, HEC_REG, 122 CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN); 123 } 124 125 static void quark_pcie_early_init(void) 126 { 127 /* 128 * Step1: Assert PCIe signal PERST# 129 * 130 * The CPU interface to the PERST# signal is platform dependent. 131 * Call the board-specific codes to perform this task. 132 */ 133 board_assert_perst(); 134 135 /* Step2: PHY common lane reset */ 136 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_PHY_LANE_RST); 137 /* wait 1 ms for PHY common lane reset */ 138 mdelay(1); 139 140 /* Step3: PHY sideband interface reset and controller main reset */ 141 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, 142 PCIE_PHY_SB_RST | PCIE_CTLR_MAIN_RST); 143 /* wait 80ms for PLL to lock */ 144 mdelay(80); 145 146 /* Step4: Controller sideband interface reset */ 147 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_CTLR_SB_RST); 148 /* wait 20ms for controller sideband interface reset */ 149 mdelay(20); 150 151 /* Step5: De-assert PERST# */ 152 board_deassert_perst(); 153 154 /* Step6: Controller primary interface reset */ 155 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_CTLR_PRI_RST); 156 157 /* Mixer Load Lane 0 */ 158 msg_port_io_clrbits(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L0, 159 (1 << 6) | (1 << 7)); 160 161 /* Mixer Load Lane 1 */ 162 msg_port_io_clrbits(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L1, 163 (1 << 6) | (1 << 7)); 164 } 165 166 static void quark_usb_early_init(void) 167 { 168 /* The sequence below comes from Quark firmware writer guide */ 169 170 msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_GLOBAL_PORT, 171 1 << 1, (1 << 6) | (1 << 7)); 172 173 msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_COMPBG, 174 (1 << 8) | (1 << 9), (1 << 7) | (1 << 10)); 175 176 msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 29); 177 178 msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL1, 1 << 1); 179 180 msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_PLL1, 181 (1 << 3) | (1 << 4) | (1 << 5), 1 << 6); 182 183 msg_port_alt_clrbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 29); 184 185 msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 24); 186 } 187 188 static void quark_thermal_early_init(void) 189 { 190 /* The sequence below comes from Quark firmware writer guide */ 191 192 /* thermal sensor mode config */ 193 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG1, 194 (1 << 3) | (1 << 4) | (1 << 5), 1 << 5); 195 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG1, 196 (1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) | 197 (1 << 12), 1 << 9); 198 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 14); 199 msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 17); 200 msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 18); 201 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG2, 0xffff, 0x011f); 202 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG3, 0xff, 0x17); 203 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG3, 204 (1 << 8) | (1 << 9), 1 << 8); 205 msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG3, 0xff000000); 206 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG4, 207 0x7ff800, 0xc8 << 11); 208 209 /* thermal monitor catastrophic trip set point (105 celsius) */ 210 msg_port_clrsetbits(MSG_PORT_RMU, TS_TRIP, 0xff, 155); 211 212 /* thermal monitor catastrophic trip clear point (0 celsius) */ 213 msg_port_clrsetbits(MSG_PORT_RMU, TS_TRIP, 0xff0000, 50 << 16); 214 215 /* take thermal sensor out of reset */ 216 msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG4, 1 << 0); 217 218 /* enable thermal monitor */ 219 msg_port_setbits(MSG_PORT_RMU, TS_MODE, 1 << 15); 220 221 /* lock all thermal configuration */ 222 msg_port_setbits(MSG_PORT_RMU, RMU_CTRL, (1 << 5) | (1 << 6)); 223 } 224 225 static void quark_enable_legacy_seg(void) 226 { 227 msg_port_setbits(MSG_PORT_HOST_BRIDGE, HMISC2, 228 HMISC2_SEGE | HMISC2_SEGF | HMISC2_SEGAB); 229 } 230 231 int arch_cpu_init(void) 232 { 233 int ret; 234 235 post_code(POST_CPU_INIT); 236 237 ret = x86_cpu_init_f(); 238 if (ret) 239 return ret; 240 241 /* 242 * Quark SoC does not support MSR MTRRs. Fixed and variable range MTRRs 243 * are accessed indirectly via the message port and not the traditional 244 * MSR mechanism. Only UC, WT and WB cache types are supported. 245 */ 246 quark_setup_mtrr(); 247 248 /* 249 * Quark SoC has some non-standard BARs (excluding PCI standard BARs) 250 * which need be initialized with suggested values 251 */ 252 quark_setup_bars(); 253 254 /* 255 * Initialize PCIe controller 256 * 257 * Quark SoC holds the PCIe controller in reset following a power on. 258 * U-Boot needs to release the PCIe controller from reset. The PCIe 259 * controller (D23:F0/F1) will not be visible in PCI configuration 260 * space and any access to its PCI configuration registers will cause 261 * system hang while it is held in reset. 262 */ 263 quark_pcie_early_init(); 264 265 /* Initialize USB2 PHY */ 266 quark_usb_early_init(); 267 268 /* Initialize thermal sensor */ 269 quark_thermal_early_init(); 270 271 /* Turn on legacy segments (A/B/E/F) decode to system RAM */ 272 quark_enable_legacy_seg(); 273 274 unprotect_spi_flash(); 275 276 return 0; 277 } 278 279 int print_cpuinfo(void) 280 { 281 post_code(POST_CPU_INFO); 282 return default_print_cpuinfo(); 283 } 284 285 void reset_cpu(ulong addr) 286 { 287 /* cold reset */ 288 x86_full_reset(); 289 } 290 291 static void quark_pcie_init(void) 292 { 293 u32 val; 294 295 /* PCIe upstream non-posted & posted request size */ 296 qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_CCFG, 297 CCFG_UPRS | CCFG_UNRS); 298 qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_CCFG, 299 CCFG_UPRS | CCFG_UNRS); 300 301 /* PCIe packet fast transmit mode (IPF) */ 302 qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MPC2, MPC2_IPF); 303 qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MPC2, MPC2_IPF); 304 305 /* PCIe message bus idle counter (SBIC) */ 306 qrk_pci_read_config_dword(QUARK_PCIE0, PCIE_RP_MBC, &val); 307 val |= MBC_SBIC; 308 qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MBC, val); 309 qrk_pci_read_config_dword(QUARK_PCIE1, PCIE_RP_MBC, &val); 310 val |= MBC_SBIC; 311 qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MBC, val); 312 } 313 314 static void quark_usb_init(void) 315 { 316 u32 bar; 317 318 /* Change USB EHCI packet buffer OUT/IN threshold */ 319 qrk_pci_read_config_dword(QUARK_USB_EHCI, PCI_BASE_ADDRESS_0, &bar); 320 writel((0x7f << 16) | 0x7f, bar + EHCI_INSNREG01); 321 322 /* Disable USB device interrupts */ 323 qrk_pci_read_config_dword(QUARK_USB_DEVICE, PCI_BASE_ADDRESS_0, &bar); 324 writel(0x7f, bar + USBD_INT_MASK); 325 writel((0xf << 16) | 0xf, bar + USBD_EP_INT_MASK); 326 writel((0xf << 16) | 0xf, bar + USBD_EP_INT_STS); 327 } 328 329 int arch_early_init_r(void) 330 { 331 quark_pcie_init(); 332 333 quark_usb_init(); 334 335 return 0; 336 } 337 338 int cpu_mmc_init(bd_t *bis) 339 { 340 return pci_mmc_init("Quark SDHCI", mmc_supported, 341 ARRAY_SIZE(mmc_supported)); 342 } 343 344 void cpu_irq_init(void) 345 { 346 struct quark_rcba *rcba; 347 u32 base; 348 349 qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base); 350 base &= ~MEM_BAR_EN; 351 rcba = (struct quark_rcba *)base; 352 353 /* 354 * Route Quark PCI device interrupt pin to PIRQ 355 * 356 * Route device#23's INTA/B/C/D to PIRQA/B/C/D 357 * Route device#20,21's INTA/B/C/D to PIRQE/F/G/H 358 */ 359 writew(PIRQC, &rcba->rmu_ir); 360 writew(PIRQA | (PIRQB << 4) | (PIRQC << 8) | (PIRQD << 12), 361 &rcba->d23_ir); 362 writew(PIRQD, &rcba->core_ir); 363 writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12), 364 &rcba->d20d21_ir); 365 } 366 367 int arch_misc_init(void) 368 { 369 #ifdef CONFIG_ENABLE_MRC_CACHE 370 /* 371 * We intend not to check any return value here, as even MRC cache 372 * is not saved successfully, it is not a severe error that will 373 * prevent system from continuing to boot. 374 */ 375 mrccache_save(); 376 #endif 377 378 return pirq_init(); 379 } 380 381 void board_final_cleanup(void) 382 { 383 struct quark_rcba *rcba; 384 u32 base, val; 385 386 qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base); 387 base &= ~MEM_BAR_EN; 388 rcba = (struct quark_rcba *)base; 389 390 /* Initialize 'Component ID' to zero */ 391 val = readl(&rcba->esd); 392 val &= ~0xff0000; 393 writel(val, &rcba->esd); 394 395 /* Lock HMBOUND for security */ 396 msg_port_setbits(MSG_PORT_HOST_BRIDGE, HM_BOUND, HM_BOUND_LOCK); 397 398 return; 399 } 400 401 int reserve_arch(void) 402 { 403 #ifdef CONFIG_ENABLE_MRC_CACHE 404 return mrccache_reserve(); 405 #else 406 return 0; 407 #endif 408 } 409