1 /* 2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <mmc.h> 9 #include <asm/io.h> 10 #include <asm/irq.h> 11 #include <asm/mtrr.h> 12 #include <asm/pci.h> 13 #include <asm/post.h> 14 #include <asm/processor.h> 15 #include <asm/arch/device.h> 16 #include <asm/arch/msg_port.h> 17 #include <asm/arch/quark.h> 18 19 static struct pci_device_id mmc_supported[] = { 20 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_SDIO }, 21 }; 22 23 /* 24 * TODO: 25 * 26 * This whole routine should be removed until we fully convert the ICH SPI 27 * driver to DM and make use of DT to pass the bios control register offset 28 */ 29 static void unprotect_spi_flash(void) 30 { 31 u32 bc; 32 33 qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, 0xd8, &bc); 34 bc |= 0x1; /* unprotect the flash */ 35 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, 0xd8, bc); 36 } 37 38 static void quark_setup_mtrr(void) 39 { 40 u32 base, mask; 41 int i; 42 43 disable_caches(); 44 45 /* mark the VGA RAM area as uncacheable */ 46 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_A0000, 47 MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE)); 48 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_B0000, 49 MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE)); 50 51 /* mark other fixed range areas as cacheable */ 52 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_64K_00000, 53 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); 54 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_64K_40000, 55 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); 56 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_80000, 57 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); 58 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_90000, 59 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); 60 for (i = MTRR_FIX_4K_C0000; i <= MTRR_FIX_4K_FC000; i++) 61 msg_port_write(MSG_PORT_HOST_BRIDGE, i, 62 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); 63 64 /* variable range MTRR#0: ROM area */ 65 mask = ~(CONFIG_SYS_MONITOR_LEN - 1); 66 base = CONFIG_SYS_TEXT_BASE & mask; 67 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_ROM), 68 base | MTRR_TYPE_WRBACK); 69 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_ROM), 70 mask | MTRR_PHYS_MASK_VALID); 71 72 /* variable range MTRR#1: eSRAM area */ 73 mask = ~(ESRAM_SIZE - 1); 74 base = CONFIG_ESRAM_BASE & mask; 75 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_ESRAM), 76 base | MTRR_TYPE_WRBACK); 77 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_ESRAM), 78 mask | MTRR_PHYS_MASK_VALID); 79 80 /* enable both variable and fixed range MTRRs */ 81 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_DEF_TYPE, 82 MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN); 83 84 enable_caches(); 85 } 86 87 static void quark_setup_bars(void) 88 { 89 /* GPIO - D31:F0:R44h */ 90 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA, 91 CONFIG_GPIO_BASE | IO_BAR_EN); 92 93 /* ACPI PM1 Block - D31:F0:R48h */ 94 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_PM1BLK, 95 CONFIG_ACPI_PM1_BASE | IO_BAR_EN); 96 97 /* GPE0 - D31:F0:R4Ch */ 98 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GPE0BLK, 99 CONFIG_ACPI_GPE0_BASE | IO_BAR_EN); 100 101 /* WDT - D31:F0:R84h */ 102 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_WDTBA, 103 CONFIG_WDT_BASE | IO_BAR_EN); 104 105 /* RCBA - D31:F0:RF0h */ 106 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, 107 CONFIG_RCBA_BASE | MEM_BAR_EN); 108 109 /* ACPI P Block - Msg Port 04:R70h */ 110 msg_port_write(MSG_PORT_RMU, PBLK_BA, 111 CONFIG_ACPI_PBLK_BASE | IO_BAR_EN); 112 113 /* SPI DMA - Msg Port 04:R7Ah */ 114 msg_port_write(MSG_PORT_RMU, SPI_DMA_BA, 115 CONFIG_SPI_DMA_BASE | IO_BAR_EN); 116 117 /* PCIe ECAM */ 118 msg_port_write(MSG_PORT_MEM_ARBITER, AEC_CTRL, 119 CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN); 120 msg_port_write(MSG_PORT_HOST_BRIDGE, HEC_REG, 121 CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN); 122 } 123 124 static void quark_pcie_early_init(void) 125 { 126 /* 127 * Step1: Assert PCIe signal PERST# 128 * 129 * The CPU interface to the PERST# signal is platform dependent. 130 * Call the board-specific codes to perform this task. 131 */ 132 board_assert_perst(); 133 134 /* Step2: PHY common lane reset */ 135 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_PHY_LANE_RST); 136 /* wait 1 ms for PHY common lane reset */ 137 mdelay(1); 138 139 /* Step3: PHY sideband interface reset and controller main reset */ 140 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, 141 PCIE_PHY_SB_RST | PCIE_CTLR_MAIN_RST); 142 /* wait 80ms for PLL to lock */ 143 mdelay(80); 144 145 /* Step4: Controller sideband interface reset */ 146 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_CTLR_SB_RST); 147 /* wait 20ms for controller sideband interface reset */ 148 mdelay(20); 149 150 /* Step5: De-assert PERST# */ 151 board_deassert_perst(); 152 153 /* Step6: Controller primary interface reset */ 154 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_CTLR_PRI_RST); 155 156 /* Mixer Load Lane 0 */ 157 msg_port_io_clrbits(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L0, 158 (1 << 6) | (1 << 7)); 159 160 /* Mixer Load Lane 1 */ 161 msg_port_io_clrbits(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L1, 162 (1 << 6) | (1 << 7)); 163 } 164 165 static void quark_usb_early_init(void) 166 { 167 /* The sequence below comes from Quark firmware writer guide */ 168 169 msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_GLOBAL_PORT, 170 1 << 1, (1 << 6) | (1 << 7)); 171 172 msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_COMPBG, 173 (1 << 8) | (1 << 9), (1 << 7) | (1 << 10)); 174 175 msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 29); 176 177 msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL1, 1 << 1); 178 179 msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_PLL1, 180 (1 << 3) | (1 << 4) | (1 << 5), 1 << 6); 181 182 msg_port_alt_clrbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 29); 183 184 msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 24); 185 } 186 187 static void quark_thermal_early_init(void) 188 { 189 /* The sequence below comes from Quark firmware writer guide */ 190 191 /* thermal sensor mode config */ 192 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG1, 193 (1 << 3) | (1 << 4) | (1 << 5), 1 << 5); 194 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG1, 195 (1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) | 196 (1 << 12), 1 << 9); 197 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 14); 198 msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 17); 199 msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 18); 200 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG2, 0xffff, 0x011f); 201 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG3, 0xff, 0x17); 202 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG3, 203 (1 << 8) | (1 << 9), 1 << 8); 204 msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG3, 0xff000000); 205 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG4, 206 0x7ff800, 0xc8 << 11); 207 208 /* thermal monitor catastrophic trip set point (105 celsius) */ 209 msg_port_clrsetbits(MSG_PORT_RMU, TS_TRIP, 0xff, 155); 210 211 /* thermal monitor catastrophic trip clear point (0 celsius) */ 212 msg_port_clrsetbits(MSG_PORT_RMU, TS_TRIP, 0xff0000, 50 << 16); 213 214 /* take thermal sensor out of reset */ 215 msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG4, 1 << 0); 216 217 /* enable thermal monitor */ 218 msg_port_setbits(MSG_PORT_RMU, TS_MODE, 1 << 15); 219 220 /* lock all thermal configuration */ 221 msg_port_setbits(MSG_PORT_RMU, RMU_CTRL, (1 << 5) | (1 << 6)); 222 } 223 224 static void quark_enable_legacy_seg(void) 225 { 226 msg_port_setbits(MSG_PORT_HOST_BRIDGE, HMISC2, 227 HMISC2_SEGE | HMISC2_SEGF | HMISC2_SEGAB); 228 } 229 230 int arch_cpu_init(void) 231 { 232 int ret; 233 234 post_code(POST_CPU_INIT); 235 #ifdef CONFIG_SYS_X86_TSC_TIMER 236 timer_set_base(rdtsc()); 237 #endif 238 239 ret = x86_cpu_init_f(); 240 if (ret) 241 return ret; 242 243 /* 244 * Quark SoC does not support MSR MTRRs. Fixed and variable range MTRRs 245 * are accessed indirectly via the message port and not the traditional 246 * MSR mechanism. Only UC, WT and WB cache types are supported. 247 */ 248 quark_setup_mtrr(); 249 250 /* 251 * Quark SoC has some non-standard BARs (excluding PCI standard BARs) 252 * which need be initialized with suggested values 253 */ 254 quark_setup_bars(); 255 256 /* 257 * Initialize PCIe controller 258 * 259 * Quark SoC holds the PCIe controller in reset following a power on. 260 * U-Boot needs to release the PCIe controller from reset. The PCIe 261 * controller (D23:F0/F1) will not be visible in PCI configuration 262 * space and any access to its PCI configuration registers will cause 263 * system hang while it is held in reset. 264 */ 265 quark_pcie_early_init(); 266 267 /* Initialize USB2 PHY */ 268 quark_usb_early_init(); 269 270 /* Initialize thermal sensor */ 271 quark_thermal_early_init(); 272 273 /* Turn on legacy segments (A/B/E/F) decode to system RAM */ 274 quark_enable_legacy_seg(); 275 276 unprotect_spi_flash(); 277 278 return 0; 279 } 280 281 int print_cpuinfo(void) 282 { 283 post_code(POST_CPU_INFO); 284 return default_print_cpuinfo(); 285 } 286 287 void reset_cpu(ulong addr) 288 { 289 /* cold reset */ 290 x86_full_reset(); 291 } 292 293 static void quark_pcie_init(void) 294 { 295 u32 val; 296 297 /* PCIe upstream non-posted & posted request size */ 298 qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_CCFG, 299 CCFG_UPRS | CCFG_UNRS); 300 qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_CCFG, 301 CCFG_UPRS | CCFG_UNRS); 302 303 /* PCIe packet fast transmit mode (IPF) */ 304 qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MPC2, MPC2_IPF); 305 qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MPC2, MPC2_IPF); 306 307 /* PCIe message bus idle counter (SBIC) */ 308 qrk_pci_read_config_dword(QUARK_PCIE0, PCIE_RP_MBC, &val); 309 val |= MBC_SBIC; 310 qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MBC, val); 311 qrk_pci_read_config_dword(QUARK_PCIE1, PCIE_RP_MBC, &val); 312 val |= MBC_SBIC; 313 qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MBC, val); 314 } 315 316 static void quark_usb_init(void) 317 { 318 u32 bar; 319 320 /* Change USB EHCI packet buffer OUT/IN threshold */ 321 qrk_pci_read_config_dword(QUARK_USB_EHCI, PCI_BASE_ADDRESS_0, &bar); 322 writel((0x7f << 16) | 0x7f, bar + EHCI_INSNREG01); 323 324 /* Disable USB device interrupts */ 325 qrk_pci_read_config_dword(QUARK_USB_DEVICE, PCI_BASE_ADDRESS_0, &bar); 326 writel(0x7f, bar + USBD_INT_MASK); 327 writel((0xf << 16) | 0xf, bar + USBD_EP_INT_MASK); 328 writel((0xf << 16) | 0xf, bar + USBD_EP_INT_STS); 329 } 330 331 int arch_early_init_r(void) 332 { 333 quark_pcie_init(); 334 335 quark_usb_init(); 336 337 return 0; 338 } 339 340 int cpu_mmc_init(bd_t *bis) 341 { 342 return pci_mmc_init("Quark SDHCI", mmc_supported, 343 ARRAY_SIZE(mmc_supported)); 344 } 345 346 void cpu_irq_init(void) 347 { 348 struct quark_rcba *rcba; 349 u32 base; 350 351 qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base); 352 base &= ~MEM_BAR_EN; 353 rcba = (struct quark_rcba *)base; 354 355 /* 356 * Route Quark PCI device interrupt pin to PIRQ 357 * 358 * Route device#23's INTA/B/C/D to PIRQA/B/C/D 359 * Route device#20,21's INTA/B/C/D to PIRQE/F/G/H 360 */ 361 writew(PIRQC, &rcba->rmu_ir); 362 writew(PIRQA | (PIRQB << 4) | (PIRQC << 8) | (PIRQD << 12), 363 &rcba->d23_ir); 364 writew(PIRQD, &rcba->core_ir); 365 writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12), 366 &rcba->d20d21_ir); 367 } 368 369 int arch_misc_init(void) 370 { 371 return pirq_init(); 372 } 373 374 void board_final_cleanup(void) 375 { 376 struct quark_rcba *rcba; 377 u32 base, val; 378 379 qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base); 380 base &= ~MEM_BAR_EN; 381 rcba = (struct quark_rcba *)base; 382 383 /* Initialize 'Component ID' to zero */ 384 val = readl(&rcba->esd); 385 val &= ~0xff0000; 386 writel(val, &rcba->esd); 387 388 /* Lock HMBOUND for security */ 389 msg_port_setbits(MSG_PORT_HOST_BRIDGE, HM_BOUND, HM_BOUND_LOCK); 390 391 return; 392 } 393