1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 4 */ 5 6 #include <common.h> 7 #include <mmc.h> 8 #include <asm/io.h> 9 #include <asm/ioapic.h> 10 #include <asm/mrccache.h> 11 #include <asm/mtrr.h> 12 #include <asm/pci.h> 13 #include <asm/post.h> 14 #include <asm/arch/device.h> 15 #include <asm/arch/msg_port.h> 16 #include <asm/arch/quark.h> 17 18 static void quark_setup_mtrr(void) 19 { 20 u32 base, mask; 21 int i; 22 23 disable_caches(); 24 25 /* mark the VGA RAM area as uncacheable */ 26 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_A0000, 27 MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE)); 28 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_B0000, 29 MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE)); 30 31 /* mark other fixed range areas as cacheable */ 32 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_64K_00000, 33 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); 34 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_64K_40000, 35 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); 36 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_80000, 37 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); 38 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_90000, 39 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); 40 for (i = MTRR_FIX_4K_C0000; i <= MTRR_FIX_4K_FC000; i++) 41 msg_port_write(MSG_PORT_HOST_BRIDGE, i, 42 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); 43 44 /* variable range MTRR#0: ROM area */ 45 mask = ~(CONFIG_SYS_MONITOR_LEN - 1); 46 base = CONFIG_SYS_TEXT_BASE & mask; 47 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_ROM), 48 base | MTRR_TYPE_WRBACK); 49 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_ROM), 50 mask | MTRR_PHYS_MASK_VALID); 51 52 /* variable range MTRR#1: eSRAM area */ 53 mask = ~(ESRAM_SIZE - 1); 54 base = CONFIG_ESRAM_BASE & mask; 55 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_ESRAM), 56 base | MTRR_TYPE_WRBACK); 57 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_ESRAM), 58 mask | MTRR_PHYS_MASK_VALID); 59 60 /* enable both variable and fixed range MTRRs */ 61 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_DEF_TYPE, 62 MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN); 63 64 enable_caches(); 65 } 66 67 static void quark_setup_bars(void) 68 { 69 /* GPIO - D31:F0:R44h */ 70 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA, 71 CONFIG_GPIO_BASE | IO_BAR_EN); 72 73 /* ACPI PM1 Block - D31:F0:R48h */ 74 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_PM1BLK, 75 CONFIG_ACPI_PM1_BASE | IO_BAR_EN); 76 77 /* GPE0 - D31:F0:R4Ch */ 78 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GPE0BLK, 79 CONFIG_ACPI_GPE0_BASE | IO_BAR_EN); 80 81 /* WDT - D31:F0:R84h */ 82 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_WDTBA, 83 CONFIG_WDT_BASE | IO_BAR_EN); 84 85 /* RCBA - D31:F0:RF0h */ 86 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, 87 CONFIG_RCBA_BASE | MEM_BAR_EN); 88 89 /* ACPI P Block - Msg Port 04:R70h */ 90 msg_port_write(MSG_PORT_RMU, PBLK_BA, 91 CONFIG_ACPI_PBLK_BASE | IO_BAR_EN); 92 93 /* SPI DMA - Msg Port 04:R7Ah */ 94 msg_port_write(MSG_PORT_RMU, SPI_DMA_BA, 95 CONFIG_SPI_DMA_BASE | IO_BAR_EN); 96 97 /* PCIe ECAM */ 98 msg_port_write(MSG_PORT_MEM_ARBITER, AEC_CTRL, 99 CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN); 100 msg_port_write(MSG_PORT_HOST_BRIDGE, HEC_REG, 101 CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN); 102 } 103 104 static void quark_pcie_early_init(void) 105 { 106 /* 107 * Step1: Assert PCIe signal PERST# 108 * 109 * The CPU interface to the PERST# signal is platform dependent. 110 * Call the board-specific codes to perform this task. 111 */ 112 board_assert_perst(); 113 114 /* Step2: PHY common lane reset */ 115 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_PHY_LANE_RST); 116 /* wait 1 ms for PHY common lane reset */ 117 mdelay(1); 118 119 /* Step3: PHY sideband interface reset and controller main reset */ 120 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, 121 PCIE_PHY_SB_RST | PCIE_CTLR_MAIN_RST); 122 /* wait 80ms for PLL to lock */ 123 mdelay(80); 124 125 /* Step4: Controller sideband interface reset */ 126 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_CTLR_SB_RST); 127 /* wait 20ms for controller sideband interface reset */ 128 mdelay(20); 129 130 /* Step5: De-assert PERST# */ 131 board_deassert_perst(); 132 133 /* Step6: Controller primary interface reset */ 134 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_CTLR_PRI_RST); 135 136 /* Mixer Load Lane 0 */ 137 msg_port_io_clrbits(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L0, 138 (1 << 6) | (1 << 7)); 139 140 /* Mixer Load Lane 1 */ 141 msg_port_io_clrbits(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L1, 142 (1 << 6) | (1 << 7)); 143 } 144 145 static void quark_usb_early_init(void) 146 { 147 /* The sequence below comes from Quark firmware writer guide */ 148 149 msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_GLOBAL_PORT, 150 1 << 1, (1 << 6) | (1 << 7)); 151 152 msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_COMPBG, 153 (1 << 8) | (1 << 9), (1 << 7) | (1 << 10)); 154 155 msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 29); 156 157 msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL1, 1 << 1); 158 159 msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_PLL1, 160 (1 << 3) | (1 << 4) | (1 << 5), 1 << 6); 161 162 msg_port_alt_clrbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 29); 163 164 msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 24); 165 } 166 167 static void quark_thermal_early_init(void) 168 { 169 /* The sequence below comes from Quark firmware writer guide */ 170 171 /* thermal sensor mode config */ 172 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG1, 173 (1 << 3) | (1 << 4) | (1 << 5), 1 << 5); 174 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG1, 175 (1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) | 176 (1 << 12), 1 << 9); 177 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 14); 178 msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 17); 179 msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 18); 180 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG2, 0xffff, 0x011f); 181 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG3, 0xff, 0x17); 182 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG3, 183 (1 << 8) | (1 << 9), 1 << 8); 184 msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG3, 0xff000000); 185 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG4, 186 0x7ff800, 0xc8 << 11); 187 188 /* thermal monitor catastrophic trip set point (105 celsius) */ 189 msg_port_clrsetbits(MSG_PORT_RMU, TS_TRIP, 0xff, 155); 190 191 /* thermal monitor catastrophic trip clear point (0 celsius) */ 192 msg_port_clrsetbits(MSG_PORT_RMU, TS_TRIP, 0xff0000, 50 << 16); 193 194 /* take thermal sensor out of reset */ 195 msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG4, 1 << 0); 196 197 /* enable thermal monitor */ 198 msg_port_setbits(MSG_PORT_RMU, TS_MODE, 1 << 15); 199 200 /* lock all thermal configuration */ 201 msg_port_setbits(MSG_PORT_RMU, RMU_CTRL, (1 << 5) | (1 << 6)); 202 } 203 204 static void quark_enable_legacy_seg(void) 205 { 206 msg_port_setbits(MSG_PORT_HOST_BRIDGE, HMISC2, 207 HMISC2_SEGE | HMISC2_SEGF | HMISC2_SEGAB); 208 } 209 210 int arch_cpu_init(void) 211 { 212 int ret; 213 214 post_code(POST_CPU_INIT); 215 216 ret = x86_cpu_init_f(); 217 if (ret) 218 return ret; 219 220 /* 221 * Quark SoC does not support MSR MTRRs. Fixed and variable range MTRRs 222 * are accessed indirectly via the message port and not the traditional 223 * MSR mechanism. Only UC, WT and WB cache types are supported. 224 */ 225 quark_setup_mtrr(); 226 227 /* 228 * Quark SoC has some non-standard BARs (excluding PCI standard BARs) 229 * which need be initialized with suggested values 230 */ 231 quark_setup_bars(); 232 233 /* Initialize USB2 PHY */ 234 quark_usb_early_init(); 235 236 /* Initialize thermal sensor */ 237 quark_thermal_early_init(); 238 239 /* Turn on legacy segments (A/B/E/F) decode to system RAM */ 240 quark_enable_legacy_seg(); 241 242 return 0; 243 } 244 245 int arch_cpu_init_dm(void) 246 { 247 /* 248 * Initialize PCIe controller 249 * 250 * Quark SoC holds the PCIe controller in reset following a power on. 251 * U-Boot needs to release the PCIe controller from reset. The PCIe 252 * controller (D23:F0/F1) will not be visible in PCI configuration 253 * space and any access to its PCI configuration registers will cause 254 * system hang while it is held in reset. 255 */ 256 quark_pcie_early_init(); 257 258 return 0; 259 } 260 261 int checkcpu(void) 262 { 263 return 0; 264 } 265 266 int print_cpuinfo(void) 267 { 268 post_code(POST_CPU_INFO); 269 return default_print_cpuinfo(); 270 } 271 272 void reset_cpu(ulong addr) 273 { 274 /* cold reset */ 275 x86_full_reset(); 276 } 277 278 static void quark_pcie_init(void) 279 { 280 u32 val; 281 282 /* PCIe upstream non-posted & posted request size */ 283 qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_CCFG, 284 CCFG_UPRS | CCFG_UNRS); 285 qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_CCFG, 286 CCFG_UPRS | CCFG_UNRS); 287 288 /* PCIe packet fast transmit mode (IPF) */ 289 qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MPC2, MPC2_IPF); 290 qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MPC2, MPC2_IPF); 291 292 /* PCIe message bus idle counter (SBIC) */ 293 qrk_pci_read_config_dword(QUARK_PCIE0, PCIE_RP_MBC, &val); 294 val |= MBC_SBIC; 295 qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MBC, val); 296 qrk_pci_read_config_dword(QUARK_PCIE1, PCIE_RP_MBC, &val); 297 val |= MBC_SBIC; 298 qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MBC, val); 299 } 300 301 static void quark_usb_init(void) 302 { 303 u32 bar; 304 305 /* Change USB EHCI packet buffer OUT/IN threshold */ 306 qrk_pci_read_config_dword(QUARK_USB_EHCI, PCI_BASE_ADDRESS_0, &bar); 307 writel((0x7f << 16) | 0x7f, bar + EHCI_INSNREG01); 308 309 /* Disable USB device interrupts */ 310 qrk_pci_read_config_dword(QUARK_USB_DEVICE, PCI_BASE_ADDRESS_0, &bar); 311 writel(0x7f, bar + USBD_INT_MASK); 312 writel((0xf << 16) | 0xf, bar + USBD_EP_INT_MASK); 313 writel((0xf << 16) | 0xf, bar + USBD_EP_INT_STS); 314 } 315 316 int arch_early_init_r(void) 317 { 318 quark_pcie_init(); 319 320 quark_usb_init(); 321 322 return 0; 323 } 324 325 int arch_misc_init(void) 326 { 327 #ifdef CONFIG_ENABLE_MRC_CACHE 328 /* 329 * We intend not to check any return value here, as even MRC cache 330 * is not saved successfully, it is not a severe error that will 331 * prevent system from continuing to boot. 332 */ 333 mrccache_save(); 334 #endif 335 336 /* Assign a unique I/O APIC ID */ 337 io_apic_set_id(1); 338 339 return 0; 340 } 341 342 void board_final_cleanup(void) 343 { 344 struct quark_rcba *rcba; 345 u32 base, val; 346 347 qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base); 348 base &= ~MEM_BAR_EN; 349 rcba = (struct quark_rcba *)base; 350 351 /* Initialize 'Component ID' to zero */ 352 val = readl(&rcba->esd); 353 val &= ~0xff0000; 354 writel(val, &rcba->esd); 355 356 /* Lock HMBOUND for security */ 357 msg_port_setbits(MSG_PORT_HOST_BRIDGE, HM_BOUND, HM_BOUND_LOCK); 358 359 return; 360 } 361