1 /* 2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <mmc.h> 9 #include <netdev.h> 10 #include <phy.h> 11 #include <asm/io.h> 12 #include <asm/pci.h> 13 #include <asm/post.h> 14 #include <asm/processor.h> 15 #include <asm/arch/device.h> 16 #include <asm/arch/msg_port.h> 17 #include <asm/arch/quark.h> 18 19 static struct pci_device_id mmc_supported[] = { 20 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_SDIO }, 21 }; 22 23 /* 24 * TODO: 25 * 26 * This whole routine should be removed until we fully convert the ICH SPI 27 * driver to DM and make use of DT to pass the bios control register offset 28 */ 29 static void unprotect_spi_flash(void) 30 { 31 u32 bc; 32 33 bc = pci_read_config32(QUARK_LEGACY_BRIDGE, 0xd8); 34 bc |= 0x1; /* unprotect the flash */ 35 pci_write_config32(QUARK_LEGACY_BRIDGE, 0xd8, bc); 36 } 37 38 static void quark_setup_bars(void) 39 { 40 /* GPIO - D31:F0:R44h */ 41 pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA, 42 CONFIG_GPIO_BASE | IO_BAR_EN); 43 44 /* ACPI PM1 Block - D31:F0:R48h */ 45 pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_PM1BLK, 46 CONFIG_ACPI_PM1_BASE | IO_BAR_EN); 47 48 /* GPE0 - D31:F0:R4Ch */ 49 pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GPE0BLK, 50 CONFIG_ACPI_GPE0_BASE | IO_BAR_EN); 51 52 /* WDT - D31:F0:R84h */ 53 pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_WDTBA, 54 CONFIG_WDT_BASE | IO_BAR_EN); 55 56 /* RCBA - D31:F0:RF0h */ 57 pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, 58 CONFIG_RCBA_BASE | MEM_BAR_EN); 59 60 /* ACPI P Block - Msg Port 04:R70h */ 61 msg_port_write(MSG_PORT_RMU, PBLK_BA, 62 CONFIG_ACPI_PBLK_BASE | IO_BAR_EN); 63 64 /* SPI DMA - Msg Port 04:R7Ah */ 65 msg_port_write(MSG_PORT_RMU, SPI_DMA_BA, 66 CONFIG_SPI_DMA_BASE | IO_BAR_EN); 67 68 /* PCIe ECAM */ 69 msg_port_write(MSG_PORT_MEM_ARBITER, AEC_CTRL, 70 CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN); 71 msg_port_write(MSG_PORT_HOST_BRIDGE, HEC_REG, 72 CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN); 73 } 74 75 int arch_cpu_init(void) 76 { 77 struct pci_controller *hose; 78 int ret; 79 80 post_code(POST_CPU_INIT); 81 #ifdef CONFIG_SYS_X86_TSC_TIMER 82 timer_set_base(rdtsc()); 83 #endif 84 85 ret = x86_cpu_init_f(); 86 if (ret) 87 return ret; 88 89 ret = pci_early_init_hose(&hose); 90 if (ret) 91 return ret; 92 93 /* 94 * Quark SoC has some non-standard BARs (excluding PCI standard BARs) 95 * which need be initialized with suggested values 96 */ 97 quark_setup_bars(); 98 99 unprotect_spi_flash(); 100 101 return 0; 102 } 103 104 int print_cpuinfo(void) 105 { 106 post_code(POST_CPU_INFO); 107 return default_print_cpuinfo(); 108 } 109 110 void reset_cpu(ulong addr) 111 { 112 /* cold reset */ 113 outb(0x08, PORT_RESET); 114 } 115 116 int cpu_mmc_init(bd_t *bis) 117 { 118 return pci_mmc_init("Quark SDHCI", mmc_supported, 119 ARRAY_SIZE(mmc_supported)); 120 } 121 122 int cpu_eth_init(bd_t *bis) 123 { 124 u32 base; 125 int ret0, ret1; 126 127 pci_read_config_dword(QUARK_EMAC0, PCI_BASE_ADDRESS_0, &base); 128 ret0 = designware_initialize(base, PHY_INTERFACE_MODE_RMII); 129 130 pci_read_config_dword(QUARK_EMAC1, PCI_BASE_ADDRESS_0, &base); 131 ret1 = designware_initialize(base, PHY_INTERFACE_MODE_RMII); 132 133 if (ret0 < 0 && ret1 < 0) 134 return -1; 135 else 136 return 0; 137 } 138