1 /* 2 * Copyright (C) 2013, Intel Corporation 3 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 4 * 5 * Ported from Intel released Quark UEFI BIOS 6 * QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei 7 * 8 * SPDX-License-Identifier: Intel 9 */ 10 11 #ifndef _MRC_UTIL_H_ 12 #define _MRC_UTIL_H_ 13 14 /* Turn on this macro to enable MRC debugging output */ 15 #undef MRC_DEBUG 16 17 /* MRC Debug Support */ 18 #define DPF debug_cond 19 20 /* debug print type */ 21 22 #ifdef MRC_DEBUG 23 #define D_ERROR 0x0001 24 #define D_INFO 0x0002 25 #define D_REGRD 0x0004 26 #define D_REGWR 0x0008 27 #define D_FCALL 0x0010 28 #define D_TRN 0x0020 29 #define D_TIME 0x0040 30 #else 31 #define D_ERROR 0 32 #define D_INFO 0 33 #define D_REGRD 0 34 #define D_REGWR 0 35 #define D_FCALL 0 36 #define D_TRN 0 37 #define D_TIME 0 38 #endif 39 40 #define ENTERFN(...) debug_cond(D_FCALL, "<%s>\n", __func__) 41 #define LEAVEFN(...) debug_cond(D_FCALL, "</%s>\n", __func__) 42 #define REPORTFN(...) debug_cond(D_FCALL, "<%s/>\n", __func__) 43 44 /* Message Bus Port */ 45 #define MEM_CTLR 0x01 46 #define HOST_BRIDGE 0x03 47 #define MEM_MGR 0x05 48 #define HTE 0x11 49 #define DDRPHY 0x12 50 51 /* number of sample points */ 52 #define SAMPLE_CNT 3 53 /* number of PIs to increment per sample */ 54 #define SAMPLE_DLY 26 55 56 enum { 57 /* indicates to decrease delays when looking for edge */ 58 BACKWARD, 59 /* indicates to increase delays when looking for edge */ 60 FORWARD 61 }; 62 63 enum { 64 RCVN, 65 WDQS, 66 WDQX, 67 RDQS, 68 VREF, 69 WCMD, 70 WCTL, 71 WCLK, 72 MAX_ALGOS, 73 }; 74 75 void mrc_write_mask(u32 unit, u32 addr, u32 data, u32 mask); 76 void mrc_alt_write_mask(u32 unit, u32 addr, u32 data, u32 mask); 77 void mrc_post_code(uint8_t major, uint8_t minor); 78 void delay_n(uint32_t ns); 79 void delay_u(uint32_t ms); 80 void select_mem_mgr(void); 81 void select_hte(void); 82 void dram_init_command(uint32_t data); 83 void dram_wake_command(void); 84 void training_message(uint8_t channel, uint8_t rank, uint8_t byte_lane); 85 86 void set_rcvn(uint8_t channel, uint8_t rank, 87 uint8_t byte_lane, uint32_t pi_count); 88 uint32_t get_rcvn(uint8_t channel, uint8_t rank, uint8_t byte_lane); 89 void set_rdqs(uint8_t channel, uint8_t rank, 90 uint8_t byte_lane, uint32_t pi_count); 91 uint32_t get_rdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane); 92 void set_wdqs(uint8_t channel, uint8_t rank, 93 uint8_t byte_lane, uint32_t pi_count); 94 uint32_t get_wdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane); 95 void set_wdq(uint8_t channel, uint8_t rank, 96 uint8_t byte_lane, uint32_t pi_count); 97 uint32_t get_wdq(uint8_t channel, uint8_t rank, uint8_t byte_lane); 98 void set_wcmd(uint8_t channel, uint32_t pi_count); 99 uint32_t get_wcmd(uint8_t channel); 100 void set_wclk(uint8_t channel, uint8_t rank, uint32_t pi_count); 101 uint32_t get_wclk(uint8_t channel, uint8_t rank); 102 void set_wctl(uint8_t channel, uint8_t rank, uint32_t pi_count); 103 uint32_t get_wctl(uint8_t channel, uint8_t rank); 104 void set_vref(uint8_t channel, uint8_t byte_lane, uint32_t setting); 105 uint32_t get_vref(uint8_t channel, uint8_t byte_lane); 106 107 uint32_t get_addr(uint8_t channel, uint8_t rank); 108 uint32_t sample_dqs(struct mrc_params *mrc_params, uint8_t channel, 109 uint8_t rank, bool rcvn); 110 void find_rising_edge(struct mrc_params *mrc_params, uint32_t delay[], 111 uint8_t channel, uint8_t rank, bool rcvn); 112 uint32_t byte_lane_mask(struct mrc_params *mrc_params); 113 uint32_t check_rw_coarse(struct mrc_params *mrc_params, uint32_t address); 114 uint32_t check_bls_ex(struct mrc_params *mrc_params, uint32_t address); 115 void lfsr32(uint32_t *lfsr_ptr); 116 void clear_pointers(void); 117 void print_timings(struct mrc_params *mrc_params); 118 119 #endif /* _MRC_UTIL_H_ */ 120