1 /* 2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <errno.h> 9 #include <fdtdec.h> 10 #include <asm/mtrr.h> 11 #include <asm/post.h> 12 #include <asm/arch/mrc.h> 13 #include <asm/arch/msg_port.h> 14 #include <asm/arch/quark.h> 15 16 DECLARE_GLOBAL_DATA_PTR; 17 18 static int mrc_configure_params(struct mrc_params *mrc_params) 19 { 20 const void *blob = gd->fdt_blob; 21 int node; 22 int mrc_flags; 23 24 node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_QRK_MRC); 25 if (node < 0) { 26 debug("%s: Cannot find MRC node\n", __func__); 27 return -EINVAL; 28 } 29 30 /* 31 * TODO: 32 * 33 * We need support fast boot (MRC cache) in the future. 34 * 35 * Set boot mode to cold boot for now 36 */ 37 mrc_params->boot_mode = BM_COLD; 38 39 /* 40 * TODO: 41 * 42 * We need determine ECC by pin strap state 43 * 44 * Disable ECC by default for now 45 */ 46 mrc_params->ecc_enables = 0; 47 48 mrc_flags = fdtdec_get_int(blob, node, "flags", 0); 49 if (mrc_flags & MRC_FLAG_SCRAMBLE_EN) 50 mrc_params->scrambling_enables = 1; 51 else 52 mrc_params->scrambling_enables = 0; 53 54 mrc_params->dram_width = fdtdec_get_int(blob, node, "dram-width", 0); 55 mrc_params->ddr_speed = fdtdec_get_int(blob, node, "dram-speed", 0); 56 mrc_params->ddr_type = fdtdec_get_int(blob, node, "dram-type", 0); 57 58 mrc_params->rank_enables = fdtdec_get_int(blob, node, "rank-mask", 0); 59 mrc_params->channel_enables = fdtdec_get_int(blob, node, 60 "chan-mask", 0); 61 mrc_params->channel_width = fdtdec_get_int(blob, node, 62 "chan-width", 0); 63 mrc_params->address_mode = fdtdec_get_int(blob, node, "addr-mode", 0); 64 65 mrc_params->refresh_rate = fdtdec_get_int(blob, node, 66 "refresh-rate", 0); 67 mrc_params->sr_temp_range = fdtdec_get_int(blob, node, 68 "sr-temp-range", 0); 69 mrc_params->ron_value = fdtdec_get_int(blob, node, 70 "ron-value", 0); 71 mrc_params->rtt_nom_value = fdtdec_get_int(blob, node, 72 "rtt-nom-value", 0); 73 mrc_params->rd_odt_value = fdtdec_get_int(blob, node, 74 "rd-odt-value", 0); 75 76 mrc_params->params.density = fdtdec_get_int(blob, node, 77 "dram-density", 0); 78 mrc_params->params.cl = fdtdec_get_int(blob, node, "dram-cl", 0); 79 mrc_params->params.ras = fdtdec_get_int(blob, node, "dram-ras", 0); 80 mrc_params->params.wtr = fdtdec_get_int(blob, node, "dram-wtr", 0); 81 mrc_params->params.rrd = fdtdec_get_int(blob, node, "dram-rrd", 0); 82 mrc_params->params.faw = fdtdec_get_int(blob, node, "dram-faw", 0); 83 84 debug("MRC dram_width %d\n", mrc_params->dram_width); 85 debug("MRC rank_enables %d\n", mrc_params->rank_enables); 86 debug("MRC ddr_speed %d\n", mrc_params->ddr_speed); 87 debug("MRC flags: %s\n", 88 (mrc_params->scrambling_enables) ? "SCRAMBLE_EN" : ""); 89 90 debug("MRC density=%d tCL=%d tRAS=%d tWTR=%d tRRD=%d tFAW=%d\n", 91 mrc_params->params.density, mrc_params->params.cl, 92 mrc_params->params.ras, mrc_params->params.wtr, 93 mrc_params->params.rrd, mrc_params->params.faw); 94 95 return 0; 96 } 97 98 int dram_init(void) 99 { 100 struct mrc_params mrc_params; 101 int ret; 102 103 memset(&mrc_params, 0, sizeof(struct mrc_params)); 104 ret = mrc_configure_params(&mrc_params); 105 if (ret) 106 return ret; 107 108 /* Set up the DRAM by calling the memory reference code */ 109 mrc_init(&mrc_params); 110 if (mrc_params.status) 111 return -EIO; 112 113 gd->ram_size = mrc_params.mem_size; 114 post_code(POST_DRAM); 115 116 /* variable range MTRR#2: RAM area */ 117 disable_caches(); 118 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_RAM), 119 0 | MTRR_TYPE_WRBACK); 120 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_RAM), 121 (~(gd->ram_size - 1)) | MTRR_PHYS_MASK_VALID); 122 enable_caches(); 123 124 return 0; 125 } 126 127 void dram_init_banksize(void) 128 { 129 gd->bd->bi_dram[0].start = 0; 130 gd->bd->bi_dram[0].size = gd->ram_size; 131 } 132 133 /* 134 * This function looks for the highest region of memory lower than 4GB which 135 * has enough space for U-Boot where U-Boot is aligned on a page boundary. 136 * It overrides the default implementation found elsewhere which simply 137 * picks the end of ram, wherever that may be. The location of the stack, 138 * the relocation address, and how far U-Boot is moved by relocation are 139 * set in the global data structure. 140 */ 141 ulong board_get_usable_ram_top(ulong total_size) 142 { 143 return gd->ram_size; 144 } 145