1 /* 2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <errno.h> 9 #include <fdtdec.h> 10 #include <malloc.h> 11 #include <asm/mrccache.h> 12 #include <asm/mtrr.h> 13 #include <asm/post.h> 14 #include <asm/arch/mrc.h> 15 #include <asm/arch/msg_port.h> 16 #include <asm/arch/quark.h> 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 static __maybe_unused int prepare_mrc_cache(struct mrc_params *mrc_params) 21 { 22 struct mrc_data_container *cache; 23 struct mrc_region entry; 24 int ret; 25 26 ret = mrccache_get_region(NULL, &entry); 27 if (ret) 28 return ret; 29 30 cache = mrccache_find_current(&entry); 31 if (!cache) 32 return -ENOENT; 33 34 debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__, 35 cache->data, cache->data_size, cache->checksum); 36 37 /* copy mrc cache to the mrc_params */ 38 memcpy(&mrc_params->timings, cache->data, cache->data_size); 39 40 return 0; 41 } 42 43 static int mrc_configure_params(struct mrc_params *mrc_params) 44 { 45 const void *blob = gd->fdt_blob; 46 int node; 47 int mrc_flags; 48 49 node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_QRK_MRC); 50 if (node < 0) { 51 debug("%s: Cannot find MRC node\n", __func__); 52 return -EINVAL; 53 } 54 55 #ifdef CONFIG_ENABLE_MRC_CACHE 56 mrc_params->boot_mode = prepare_mrc_cache(mrc_params); 57 if (mrc_params->boot_mode) 58 mrc_params->boot_mode = BM_COLD; 59 else 60 mrc_params->boot_mode = BM_FAST; 61 #else 62 mrc_params->boot_mode = BM_COLD; 63 #endif 64 65 /* 66 * TODO: 67 * 68 * We need determine ECC by pin strap state 69 * 70 * Disable ECC by default for now 71 */ 72 mrc_params->ecc_enables = 0; 73 74 mrc_flags = fdtdec_get_int(blob, node, "flags", 0); 75 if (mrc_flags & MRC_FLAG_SCRAMBLE_EN) 76 mrc_params->scrambling_enables = 1; 77 else 78 mrc_params->scrambling_enables = 0; 79 80 mrc_params->dram_width = fdtdec_get_int(blob, node, "dram-width", 0); 81 mrc_params->ddr_speed = fdtdec_get_int(blob, node, "dram-speed", 0); 82 mrc_params->ddr_type = fdtdec_get_int(blob, node, "dram-type", 0); 83 84 mrc_params->rank_enables = fdtdec_get_int(blob, node, "rank-mask", 0); 85 mrc_params->channel_enables = fdtdec_get_int(blob, node, 86 "chan-mask", 0); 87 mrc_params->channel_width = fdtdec_get_int(blob, node, 88 "chan-width", 0); 89 mrc_params->address_mode = fdtdec_get_int(blob, node, "addr-mode", 0); 90 91 mrc_params->refresh_rate = fdtdec_get_int(blob, node, 92 "refresh-rate", 0); 93 mrc_params->sr_temp_range = fdtdec_get_int(blob, node, 94 "sr-temp-range", 0); 95 mrc_params->ron_value = fdtdec_get_int(blob, node, 96 "ron-value", 0); 97 mrc_params->rtt_nom_value = fdtdec_get_int(blob, node, 98 "rtt-nom-value", 0); 99 mrc_params->rd_odt_value = fdtdec_get_int(blob, node, 100 "rd-odt-value", 0); 101 102 mrc_params->params.density = fdtdec_get_int(blob, node, 103 "dram-density", 0); 104 mrc_params->params.cl = fdtdec_get_int(blob, node, "dram-cl", 0); 105 mrc_params->params.ras = fdtdec_get_int(blob, node, "dram-ras", 0); 106 mrc_params->params.wtr = fdtdec_get_int(blob, node, "dram-wtr", 0); 107 mrc_params->params.rrd = fdtdec_get_int(blob, node, "dram-rrd", 0); 108 mrc_params->params.faw = fdtdec_get_int(blob, node, "dram-faw", 0); 109 110 debug("MRC dram_width %d\n", mrc_params->dram_width); 111 debug("MRC rank_enables %d\n", mrc_params->rank_enables); 112 debug("MRC ddr_speed %d\n", mrc_params->ddr_speed); 113 debug("MRC flags: %s\n", 114 (mrc_params->scrambling_enables) ? "SCRAMBLE_EN" : ""); 115 116 debug("MRC density=%d tCL=%d tRAS=%d tWTR=%d tRRD=%d tFAW=%d\n", 117 mrc_params->params.density, mrc_params->params.cl, 118 mrc_params->params.ras, mrc_params->params.wtr, 119 mrc_params->params.rrd, mrc_params->params.faw); 120 121 return 0; 122 } 123 124 int dram_init(void) 125 { 126 struct mrc_params mrc_params; 127 #ifdef CONFIG_ENABLE_MRC_CACHE 128 char *cache; 129 #endif 130 int ret; 131 132 memset(&mrc_params, 0, sizeof(struct mrc_params)); 133 ret = mrc_configure_params(&mrc_params); 134 if (ret) 135 return ret; 136 137 /* Set up the DRAM by calling the memory reference code */ 138 mrc_init(&mrc_params); 139 if (mrc_params.status) 140 return -EIO; 141 142 gd->ram_size = mrc_params.mem_size; 143 post_code(POST_DRAM); 144 145 /* variable range MTRR#2: RAM area */ 146 disable_caches(); 147 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_RAM), 148 0 | MTRR_TYPE_WRBACK); 149 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_RAM), 150 (~(gd->ram_size - 1)) | MTRR_PHYS_MASK_VALID); 151 enable_caches(); 152 153 #ifdef CONFIG_ENABLE_MRC_CACHE 154 cache = malloc(sizeof(struct mrc_timings)); 155 if (cache) { 156 memcpy(cache, &mrc_params.timings, sizeof(struct mrc_timings)); 157 gd->arch.mrc_output = cache; 158 gd->arch.mrc_output_len = sizeof(struct mrc_timings); 159 } 160 #endif 161 162 return 0; 163 } 164 165 void dram_init_banksize(void) 166 { 167 gd->bd->bi_dram[0].start = 0; 168 gd->bd->bi_dram[0].size = gd->ram_size; 169 } 170 171 /* 172 * This function looks for the highest region of memory lower than 4GB which 173 * has enough space for U-Boot where U-Boot is aligned on a page boundary. 174 * It overrides the default implementation found elsewhere which simply 175 * picks the end of ram, wherever that may be. The location of the stack, 176 * the relocation address, and how far U-Boot is moved by relocation are 177 * set in the global data structure. 178 */ 179 ulong board_get_usable_ram_top(ulong total_size) 180 { 181 return gd->ram_size; 182 } 183