1/* 2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <config.h> 8#include <asm/pci.h> 9#include <asm/post.h> 10#include <asm/arch/quark.h> 11#include <asm/arch/msg_port.h> 12 13.globl car_init 14car_init: 15 post_code(POST_CAR_START) 16 17 /* 18 * Quark SoC contains an embedded 512KiB SRAM (eSRAM) that is 19 * initialized by hardware. eSRAM is the ideal place to be used 20 * for Cache-As-RAM (CAR) before system memory is available. 21 * 22 * Relocate this eSRAM to a suitable location in the physical 23 * memory map and enable it. 24 */ 25 26 /* Host Memory Bound Register P03h:R08h */ 27 mov $((MSG_PORT_HOST_BRIDGE << 16) | (HM_BOUND << 8)), %eax 28 mov $(DRAM_BASE + DRAM_MAX_SIZE + ESRAM_SIZE), %edx 29 lea 1f, %esp 30 jmp msg_port_write 311: 32 33 /* eSRAM Block Page Control Register P05h:R82h */ 34 mov $((MSG_PORT_MEM_MGR << 16) | (ESRAM_BLK_CTRL << 8)), %eax 35 mov $(ESRAM_BLOCK_MODE | (CONFIG_ESRAM_BASE >> 24)), %edx 36 lea 2f, %esp 37 jmp msg_port_write 382: 39 40 post_code(POST_CAR_CPU_CACHE) 41 jmp car_init_ret 42 43msg_port_read: 44 /* 45 * Parameter: 46 * eax[23:16] - Message Port ID 47 * eax[15:08] - Register Address 48 * 49 * Return Value: 50 * eax - Message Port Register value 51 * 52 * Return Address: esp 53 */ 54 55 or $((MSG_OP_READ << 24) | MSG_BYTE_ENABLE), %eax 56 mov %eax, %ebx 57 58 /* Write MCR B0:D0:F0:RD0 */ 59 mov $(PCI_CFG_EN | MSG_CTRL_REG), %eax 60 mov $PCI_REG_ADDR, %dx 61 out %eax, %dx 62 mov $PCI_REG_DATA, %dx 63 mov %ebx, %eax 64 out %eax, %dx 65 66 /* Read MDR B0:D0:F0:RD4 */ 67 mov $(PCI_CFG_EN | MSG_DATA_REG), %eax 68 mov $PCI_REG_ADDR, %dx 69 out %eax, %dx 70 mov $PCI_REG_DATA, %dx 71 in %dx, %eax 72 73 jmp *%esp 74 75msg_port_write: 76 /* 77 * Parameter: 78 * eax[23:16] - Message Port ID 79 * eax[15:08] - Register Address 80 * edx - Message Port Register value to write 81 * 82 * Return Address: esp 83 */ 84 85 or $((MSG_OP_WRITE << 24) | MSG_BYTE_ENABLE), %eax 86 mov %eax, %esi 87 mov %edx, %edi 88 89 /* Write MDR B0:D0:F0:RD4 */ 90 mov $(PCI_CFG_EN | MSG_DATA_REG), %eax 91 mov $PCI_REG_ADDR, %dx 92 out %eax, %dx 93 mov $PCI_REG_DATA, %dx 94 mov %edi, %eax 95 out %eax, %dx 96 97 /* Write MCR B0:D0:F0:RD0 */ 98 mov $(PCI_CFG_EN | MSG_CTRL_REG), %eax 99 mov $PCI_REG_ADDR, %dx 100 out %eax, %dx 101 mov $PCI_REG_DATA, %dx 102 mov %esi, %eax 103 out %eax, %dx 104 105 jmp *%esp 106