xref: /openbmc/u-boot/arch/x86/cpu/quark/Kconfig (revision b3820ba9)
1# SPDX-License-Identifier: GPL-2.0+
2#
3# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
4
5config INTEL_QUARK
6	bool
7	select HAVE_RMU
8	select ARCH_EARLY_INIT_R
9	select ARCH_MISC_INIT
10	imply ENABLE_MRC_CACHE
11	imply ETH_DESIGNWARE
12	imply ICH_SPI
13	imply INTEL_ICH6_GPIO
14	imply MMC
15	imply MMC_PCI
16	imply MMC_SDHCI
17	imply MMC_SDHCI_SDMA
18	imply SPI_FLASH
19	imply SYS_NS16550
20	imply USB
21	imply USB_EHCI_HCD
22
23if INTEL_QUARK
24
25config HAVE_RMU
26	bool "Add a Remote Management Unit (RMU) binary"
27	help
28	  Select this option to add a Remote Management Unit (RMU) binary
29	  to the resulting U-Boot image. It is a data block (up to 64K) of
30	  machine-specific code which must be put in the flash for the RMU
31	  within the Quark SoC processor to access when powered up before
32	  system BIOS is executed.
33
34config RMU_FILE
35	string "Remote Management Unit (RMU) binary filename"
36	depends on HAVE_RMU
37	default "rmu.bin"
38	help
39	  The filename of the file to use as Remote Management Unit (RMU)
40	  binary in the board directory.
41
42config RMU_ADDR
43	hex "Remote Management Unit (RMU) binary location"
44	depends on HAVE_RMU
45	default 0xfff00000
46	help
47	  The location of the RMU binary is determined by a strap. It must be
48	  put in flash at a location matching the strap-determined base address.
49
50	  The default base address of 0xfff00000 indicates that the binary must
51	  be located at offset 0 from the beginning of a 1MB flash device.
52
53config HAVE_CMC
54	bool
55	default HAVE_RMU
56
57config CMC_FILE
58	string
59	depends on HAVE_CMC
60	default RMU_FILE
61
62config CMC_ADDR
63	hex
64	depends on HAVE_CMC
65	default RMU_ADDR
66
67config ESRAM_BASE
68	hex
69	default 0x80000000
70	help
71	  Embedded SRAM (eSRAM) memory-mapped base address.
72
73config PCIE_ECAM_BASE
74	hex
75	default 0xe0000000
76
77config RCBA_BASE
78	hex
79	default 0xfed1c000
80	help
81	  Root Complex register block memory-mapped base address.
82
83config ACPI_PM1_BASE
84	hex
85	default 0x1000
86	help
87	  ACPI Power Management 1 (PM1) i/o-mapped base address.
88	  This device is defined in ACPI specification, with 16 bytes in size.
89
90config ACPI_PBLK_BASE
91	hex
92	default 0x1010
93	help
94	  ACPI Processor Block (PBLK) i/o-mapped base address.
95	  This device is defined in ACPI specification, with 16 bytes in size.
96
97config SPI_DMA_BASE
98	hex
99	default 0x1020
100	help
101	  SPI DMA i/o-mapped base address.
102
103config GPIO_BASE
104	hex
105	default 0x1080
106	help
107	  GPIO i/o-mapped base address.
108
109config ACPI_GPE0_BASE
110	hex
111	default 0x1100
112	help
113	  ACPI General Purpose Event 0 (GPE0) i/o-mapped base address.
114	  This device is defined in ACPI specification, with 64 bytes in size.
115
116config WDT_BASE
117	hex
118	default 0x1140
119	help
120	  Watchdog timer i/o-mapped base address.
121
122config SYS_CAR_ADDR
123	hex
124	default ESRAM_BASE
125
126config SYS_CAR_SIZE
127	hex
128	default 0x8000
129	help
130	  Space in bytes in eSRAM used as Cache-As-ARM (CAR).
131	  Note this size must not exceed eSRAM's total size.
132
133config X86_TSC_TIMER_EARLY_FREQ
134	int
135	default 400
136
137endif
138