1 /* 2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/irq.h> 9 #include <asm/pci.h> 10 #include <asm/post.h> 11 #include <asm/processor.h> 12 #include <asm/arch/device.h> 13 #include <asm/arch/qemu.h> 14 15 static bool i440fx; 16 17 static void qemu_chipset_init(void) 18 { 19 u16 device, xbcs; 20 int pam, i; 21 22 /* 23 * i440FX and Q35 chipset have different PAM register offset, but with 24 * the same bitfield layout. Here we determine the offset based on its 25 * PCI device ID. 26 */ 27 device = x86_pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID); 28 i440fx = (device == PCI_DEVICE_ID_INTEL_82441); 29 pam = i440fx ? I440FX_PAM : Q35_PAM; 30 31 /* 32 * Initialize Programmable Attribute Map (PAM) Registers 33 * 34 * Configure legacy segments C/D/E/F to system RAM 35 */ 36 for (i = 0; i < PAM_NUM; i++) 37 x86_pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW); 38 39 if (i440fx) { 40 /* 41 * Enable legacy IDE I/O ports decode 42 * 43 * Note: QEMU always decode legacy IDE I/O port on PIIX chipset. 44 * However Linux ata_piix driver does sanity check on these two 45 * registers to see whether legacy ports decode is turned on. 46 * This is to make Linux ata_piix driver happy. 47 */ 48 x86_pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN); 49 x86_pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN); 50 51 /* Enable I/O APIC */ 52 xbcs = x86_pci_read_config16(PIIX_ISA, XBCS); 53 xbcs |= APIC_EN; 54 x86_pci_write_config16(PIIX_ISA, XBCS, xbcs); 55 } else { 56 /* Configure PCIe ECAM base address */ 57 x86_pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR, 58 CONFIG_PCIE_ECAM_BASE | BAR_EN); 59 } 60 } 61 62 int arch_cpu_init(void) 63 { 64 int ret; 65 66 post_code(POST_CPU_INIT); 67 68 ret = x86_cpu_init_f(); 69 if (ret) 70 return ret; 71 72 return 0; 73 } 74 75 #ifndef CONFIG_EFI_STUB 76 int print_cpuinfo(void) 77 { 78 post_code(POST_CPU_INFO); 79 return default_print_cpuinfo(); 80 } 81 #endif 82 83 void reset_cpu(ulong addr) 84 { 85 /* cold reset */ 86 x86_full_reset(); 87 } 88 89 int arch_early_init_r(void) 90 { 91 qemu_chipset_init(); 92 93 return 0; 94 } 95 96 int arch_misc_init(void) 97 { 98 return pirq_init(); 99 } 100 101 #ifdef CONFIG_GENERATE_MP_TABLE 102 int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq) 103 { 104 u8 irq; 105 106 if (i440fx) { 107 /* 108 * Not like most x86 platforms, the PIRQ[A-D] on PIIX3 are not 109 * connected to I/O APIC INTPIN#16-19. Instead they are routed 110 * to an irq number controled by the PIRQ routing register. 111 */ 112 irq = x86_pci_read_config8(PCI_BDF(bus, dev, func), 113 PCI_INTERRUPT_LINE); 114 } else { 115 /* 116 * ICH9's PIRQ[A-H] are not consecutive numbers from 0 to 7. 117 * PIRQ[A-D] still maps to [0-3] but PIRQ[E-H] maps to [8-11]. 118 */ 119 irq = pirq < 8 ? pirq + 16 : pirq + 12; 120 } 121 122 return irq; 123 } 124 #endif 125