1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2011 The Chromium OS Authors. 4 * (C) Copyright 2008,2009 5 * Graeme Russ, <graeme.russ@gmail.com> 6 * 7 * (C) Copyright 2002 8 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> 9 */ 10 11 #include <common.h> 12 #include <dm.h> 13 #include <errno.h> 14 #include <malloc.h> 15 #include <pci.h> 16 #include <asm/io.h> 17 #include <asm/pci.h> 18 19 int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset, 20 ulong *valuep, enum pci_size_t size) 21 { 22 outl(bdf | (offset & 0xfc) | PCI_CFG_EN, PCI_REG_ADDR); 23 switch (size) { 24 case PCI_SIZE_8: 25 *valuep = inb(PCI_REG_DATA + (offset & 3)); 26 break; 27 case PCI_SIZE_16: 28 *valuep = inw(PCI_REG_DATA + (offset & 2)); 29 break; 30 case PCI_SIZE_32: 31 *valuep = inl(PCI_REG_DATA); 32 break; 33 } 34 35 return 0; 36 } 37 38 int pci_x86_write_config(struct udevice *bus, pci_dev_t bdf, uint offset, 39 ulong value, enum pci_size_t size) 40 { 41 outl(bdf | (offset & 0xfc) | PCI_CFG_EN, PCI_REG_ADDR); 42 switch (size) { 43 case PCI_SIZE_8: 44 outb(value, PCI_REG_DATA + (offset & 3)); 45 break; 46 case PCI_SIZE_16: 47 outw(value, PCI_REG_DATA + (offset & 2)); 48 break; 49 case PCI_SIZE_32: 50 outl(value, PCI_REG_DATA); 51 break; 52 } 53 54 return 0; 55 } 56 57 void pci_assign_irqs(int bus, int device, u8 irq[4]) 58 { 59 pci_dev_t bdf; 60 int func; 61 u16 vendor; 62 u8 pin, line; 63 64 for (func = 0; func < 8; func++) { 65 bdf = PCI_BDF(bus, device, func); 66 pci_read_config16(bdf, PCI_VENDOR_ID, &vendor); 67 if (vendor == 0xffff || vendor == 0x0000) 68 continue; 69 70 pci_read_config8(bdf, PCI_INTERRUPT_PIN, &pin); 71 72 /* PCI spec says all values except 1..4 are reserved */ 73 if ((pin < 1) || (pin > 4)) 74 continue; 75 76 line = irq[pin - 1]; 77 if (!line) 78 continue; 79 80 debug("Assigning IRQ %d to PCI device %d.%x.%d (INT%c)\n", 81 line, bus, device, func, 'A' + pin - 1); 82 83 pci_write_config8(bdf, PCI_INTERRUPT_LINE, line); 84 } 85 } 86