1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * (C) Copyright 2008,2009 4 * Graeme Russ, <graeme.russ@gmail.com> 5 * 6 * (C) Copyright 2002 7 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <dm.h> 14 #include <errno.h> 15 #include <malloc.h> 16 #include <pci.h> 17 #include <asm/io.h> 18 #include <asm/pci.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset, 23 ulong *valuep, enum pci_size_t size) 24 { 25 outl(bdf | (offset & 0xfc) | PCI_CFG_EN, PCI_REG_ADDR); 26 switch (size) { 27 case PCI_SIZE_8: 28 *valuep = inb(PCI_REG_DATA + (offset & 3)); 29 break; 30 case PCI_SIZE_16: 31 *valuep = inw(PCI_REG_DATA + (offset & 2)); 32 break; 33 case PCI_SIZE_32: 34 *valuep = inl(PCI_REG_DATA); 35 break; 36 } 37 38 return 0; 39 } 40 41 int pci_x86_write_config(struct udevice *bus, pci_dev_t bdf, uint offset, 42 ulong value, enum pci_size_t size) 43 { 44 outl(bdf | (offset & 0xfc) | PCI_CFG_EN, PCI_REG_ADDR); 45 switch (size) { 46 case PCI_SIZE_8: 47 outb(value, PCI_REG_DATA + (offset & 3)); 48 break; 49 case PCI_SIZE_16: 50 outw(value, PCI_REG_DATA + (offset & 2)); 51 break; 52 case PCI_SIZE_32: 53 outl(value, PCI_REG_DATA); 54 break; 55 } 56 57 return 0; 58 } 59 60 void pci_assign_irqs(int bus, int device, u8 irq[4]) 61 { 62 pci_dev_t bdf; 63 int func; 64 u16 vendor; 65 u8 pin, line; 66 67 for (func = 0; func < 8; func++) { 68 bdf = PCI_BDF(bus, device, func); 69 pci_read_config16(bdf, PCI_VENDOR_ID, &vendor); 70 if (vendor == 0xffff || vendor == 0x0000) 71 continue; 72 73 pci_read_config8(bdf, PCI_INTERRUPT_PIN, &pin); 74 75 /* PCI spec says all values except 1..4 are reserved */ 76 if ((pin < 1) || (pin > 4)) 77 continue; 78 79 line = irq[pin - 1]; 80 if (!line) 81 continue; 82 83 debug("Assigning IRQ %d to PCI device %d.%x.%d (INT%c)\n", 84 line, bus, device, func, 'A' + pin - 1); 85 86 pci_write_config8(bdf, PCI_INTERRUPT_LINE, line); 87 } 88 } 89