1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2d188b18fSSimon Glass /* 3d188b18fSSimon Glass * Copyright (c) 2011 The Chromium OS Authors. 4d188b18fSSimon Glass * (C) Copyright 2008,2009 5d188b18fSSimon Glass * Graeme Russ, <graeme.russ@gmail.com> 6d188b18fSSimon Glass * 7d188b18fSSimon Glass * (C) Copyright 2002 8d188b18fSSimon Glass * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> 9d188b18fSSimon Glass */ 10d188b18fSSimon Glass 11d188b18fSSimon Glass #include <common.h> 12a219daeaSSimon Glass #include <dm.h> 137430f108SSimon Glass #include <errno.h> 147430f108SSimon Glass #include <malloc.h> 15d188b18fSSimon Glass #include <pci.h> 16a219daeaSSimon Glass #include <asm/io.h> 17d188b18fSSimon Glass #include <asm/pci.h> 18d188b18fSSimon Glass 19a219daeaSSimon Glass int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset, 20a219daeaSSimon Glass ulong *valuep, enum pci_size_t size) 21a219daeaSSimon Glass { 22a219daeaSSimon Glass outl(bdf | (offset & 0xfc) | PCI_CFG_EN, PCI_REG_ADDR); 23a219daeaSSimon Glass switch (size) { 24a219daeaSSimon Glass case PCI_SIZE_8: 25a219daeaSSimon Glass *valuep = inb(PCI_REG_DATA + (offset & 3)); 26a219daeaSSimon Glass break; 27a219daeaSSimon Glass case PCI_SIZE_16: 28a219daeaSSimon Glass *valuep = inw(PCI_REG_DATA + (offset & 2)); 29a219daeaSSimon Glass break; 30a219daeaSSimon Glass case PCI_SIZE_32: 31a219daeaSSimon Glass *valuep = inl(PCI_REG_DATA); 32a219daeaSSimon Glass break; 33a219daeaSSimon Glass } 34a219daeaSSimon Glass 35a219daeaSSimon Glass return 0; 36a219daeaSSimon Glass } 37a219daeaSSimon Glass 38a219daeaSSimon Glass int pci_x86_write_config(struct udevice *bus, pci_dev_t bdf, uint offset, 39a219daeaSSimon Glass ulong value, enum pci_size_t size) 40a219daeaSSimon Glass { 41a219daeaSSimon Glass outl(bdf | (offset & 0xfc) | PCI_CFG_EN, PCI_REG_ADDR); 42a219daeaSSimon Glass switch (size) { 43a219daeaSSimon Glass case PCI_SIZE_8: 44a219daeaSSimon Glass outb(value, PCI_REG_DATA + (offset & 3)); 45a219daeaSSimon Glass break; 46a219daeaSSimon Glass case PCI_SIZE_16: 47a219daeaSSimon Glass outw(value, PCI_REG_DATA + (offset & 2)); 48a219daeaSSimon Glass break; 49a219daeaSSimon Glass case PCI_SIZE_32: 50a219daeaSSimon Glass outl(value, PCI_REG_DATA); 51a219daeaSSimon Glass break; 52a219daeaSSimon Glass } 53a219daeaSSimon Glass 54a219daeaSSimon Glass return 0; 55a219daeaSSimon Glass } 56e3e7fa2cSBin Meng 5731a2dc69SBin Meng void pci_assign_irqs(int bus, int device, u8 irq[4]) 58e3e7fa2cSBin Meng { 59e3e7fa2cSBin Meng pci_dev_t bdf; 6031a2dc69SBin Meng int func; 6131a2dc69SBin Meng u16 vendor; 62e3e7fa2cSBin Meng u8 pin, line; 63e3e7fa2cSBin Meng 6431a2dc69SBin Meng for (func = 0; func < 8; func++) { 65e3e7fa2cSBin Meng bdf = PCI_BDF(bus, device, func); 6658316f9bSBin Meng pci_read_config16(bdf, PCI_VENDOR_ID, &vendor); 6731a2dc69SBin Meng if (vendor == 0xffff || vendor == 0x0000) 6831a2dc69SBin Meng continue; 69e3e7fa2cSBin Meng 7058316f9bSBin Meng pci_read_config8(bdf, PCI_INTERRUPT_PIN, &pin); 71e3e7fa2cSBin Meng 72e3e7fa2cSBin Meng /* PCI spec says all values except 1..4 are reserved */ 73e3e7fa2cSBin Meng if ((pin < 1) || (pin > 4)) 7431a2dc69SBin Meng continue; 75e3e7fa2cSBin Meng 76e3e7fa2cSBin Meng line = irq[pin - 1]; 776fc0e8a1SBin Meng if (!line) 786fc0e8a1SBin Meng continue; 79e3e7fa2cSBin Meng 80e3e7fa2cSBin Meng debug("Assigning IRQ %d to PCI device %d.%x.%d (INT%c)\n", 81e3e7fa2cSBin Meng line, bus, device, func, 'A' + pin - 1); 82e3e7fa2cSBin Meng 8358316f9bSBin Meng pci_write_config8(bdf, PCI_INTERRUPT_LINE, line); 84e3e7fa2cSBin Meng } 8531a2dc69SBin Meng } 86