1 /* 2 * Copyright (C) 2015 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Based on code from the coreboot file of the same name 7 */ 8 9 #include <common.h> 10 #include <cpu.h> 11 #include <dm.h> 12 #include <errno.h> 13 #include <malloc.h> 14 #include <asm/atomic.h> 15 #include <asm/cpu.h> 16 #include <asm/interrupt.h> 17 #include <asm/lapic.h> 18 #include <asm/mp.h> 19 #include <asm/msr.h> 20 #include <asm/mtrr.h> 21 #include <asm/processor.h> 22 #include <asm/sipi.h> 23 #include <dm/device-internal.h> 24 #include <dm/uclass-internal.h> 25 #include <linux/linkage.h> 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 /* Total CPUs include BSP */ 30 static int num_cpus; 31 32 /* This also needs to match the sipi.S assembly code for saved MSR encoding */ 33 struct saved_msr { 34 uint32_t index; 35 uint32_t lo; 36 uint32_t hi; 37 } __packed; 38 39 40 struct mp_flight_plan { 41 int num_records; 42 struct mp_flight_record *records; 43 }; 44 45 static struct mp_flight_plan mp_info; 46 47 struct cpu_map { 48 struct udevice *dev; 49 int apic_id; 50 int err_code; 51 }; 52 53 static inline void barrier_wait(atomic_t *b) 54 { 55 while (atomic_read(b) == 0) 56 asm("pause"); 57 mfence(); 58 } 59 60 static inline void release_barrier(atomic_t *b) 61 { 62 mfence(); 63 atomic_set(b, 1); 64 } 65 66 static inline void stop_this_cpu(void) 67 { 68 /* Called by an AP when it is ready to halt and wait for a new task */ 69 for (;;) 70 cpu_hlt(); 71 } 72 73 /* Returns 1 if timeout waiting for APs. 0 if target APs found */ 74 static int wait_for_aps(atomic_t *val, int target, int total_delay, 75 int delay_step) 76 { 77 int timeout = 0; 78 int delayed = 0; 79 80 while (atomic_read(val) != target) { 81 udelay(delay_step); 82 delayed += delay_step; 83 if (delayed >= total_delay) { 84 timeout = 1; 85 break; 86 } 87 } 88 89 return timeout; 90 } 91 92 static void ap_do_flight_plan(struct udevice *cpu) 93 { 94 int i; 95 96 for (i = 0; i < mp_info.num_records; i++) { 97 struct mp_flight_record *rec = &mp_info.records[i]; 98 99 atomic_inc(&rec->cpus_entered); 100 barrier_wait(&rec->barrier); 101 102 if (rec->ap_call != NULL) 103 rec->ap_call(cpu, rec->ap_arg); 104 } 105 } 106 107 static int find_cpu_by_apid_id(int apic_id, struct udevice **devp) 108 { 109 struct udevice *dev; 110 111 *devp = NULL; 112 for (uclass_find_first_device(UCLASS_CPU, &dev); 113 dev; 114 uclass_find_next_device(&dev)) { 115 struct cpu_platdata *plat = dev_get_parent_platdata(dev); 116 117 if (plat->cpu_id == apic_id) { 118 *devp = dev; 119 return 0; 120 } 121 } 122 123 return -ENOENT; 124 } 125 126 /* 127 * By the time APs call ap_init() caching has been setup, and microcode has 128 * been loaded 129 */ 130 static void ap_init(unsigned int cpu_index) 131 { 132 struct udevice *dev; 133 int apic_id; 134 int ret; 135 136 /* Ensure the local apic is enabled */ 137 enable_lapic(); 138 139 apic_id = lapicid(); 140 ret = find_cpu_by_apid_id(apic_id, &dev); 141 if (ret) { 142 debug("Unknown CPU apic_id %x\n", apic_id); 143 goto done; 144 } 145 146 debug("AP: slot %d apic_id %x, dev %s\n", cpu_index, apic_id, 147 dev ? dev->name : "(apic_id not found)"); 148 149 /* Walk the flight plan */ 150 ap_do_flight_plan(dev); 151 152 /* Park the AP */ 153 debug("parking\n"); 154 done: 155 stop_this_cpu(); 156 } 157 158 static const unsigned int fixed_mtrrs[NUM_FIXED_MTRRS] = { 159 MTRR_FIX_64K_00000_MSR, MTRR_FIX_16K_80000_MSR, MTRR_FIX_16K_A0000_MSR, 160 MTRR_FIX_4K_C0000_MSR, MTRR_FIX_4K_C8000_MSR, MTRR_FIX_4K_D0000_MSR, 161 MTRR_FIX_4K_D8000_MSR, MTRR_FIX_4K_E0000_MSR, MTRR_FIX_4K_E8000_MSR, 162 MTRR_FIX_4K_F0000_MSR, MTRR_FIX_4K_F8000_MSR, 163 }; 164 165 static inline struct saved_msr *save_msr(int index, struct saved_msr *entry) 166 { 167 msr_t msr; 168 169 msr = msr_read(index); 170 entry->index = index; 171 entry->lo = msr.lo; 172 entry->hi = msr.hi; 173 174 /* Return the next entry */ 175 entry++; 176 return entry; 177 } 178 179 static int save_bsp_msrs(char *start, int size) 180 { 181 int msr_count; 182 int num_var_mtrrs; 183 struct saved_msr *msr_entry; 184 int i; 185 msr_t msr; 186 187 /* Determine number of MTRRs need to be saved */ 188 msr = msr_read(MTRR_CAP_MSR); 189 num_var_mtrrs = msr.lo & 0xff; 190 191 /* 2 * num_var_mtrrs for base and mask. +1 for IA32_MTRR_DEF_TYPE */ 192 msr_count = 2 * num_var_mtrrs + NUM_FIXED_MTRRS + 1; 193 194 if ((msr_count * sizeof(struct saved_msr)) > size) { 195 printf("Cannot mirror all %d msrs.\n", msr_count); 196 return -ENOSPC; 197 } 198 199 msr_entry = (void *)start; 200 for (i = 0; i < NUM_FIXED_MTRRS; i++) 201 msr_entry = save_msr(fixed_mtrrs[i], msr_entry); 202 203 for (i = 0; i < num_var_mtrrs; i++) { 204 msr_entry = save_msr(MTRR_PHYS_BASE_MSR(i), msr_entry); 205 msr_entry = save_msr(MTRR_PHYS_MASK_MSR(i), msr_entry); 206 } 207 208 msr_entry = save_msr(MTRR_DEF_TYPE_MSR, msr_entry); 209 210 return msr_count; 211 } 212 213 static int load_sipi_vector(atomic_t **ap_countp) 214 { 215 struct sipi_params_16bit *params16; 216 struct sipi_params *params; 217 static char msr_save[512]; 218 char *stack; 219 ulong addr; 220 int code_len; 221 int size; 222 int ret; 223 224 /* Copy in the code */ 225 code_len = ap_start16_code_end - ap_start16; 226 debug("Copying SIPI code to %x: %d bytes\n", AP_DEFAULT_BASE, 227 code_len); 228 memcpy((void *)AP_DEFAULT_BASE, ap_start16, code_len); 229 230 addr = AP_DEFAULT_BASE + (ulong)sipi_params_16bit - (ulong)ap_start16; 231 params16 = (struct sipi_params_16bit *)addr; 232 params16->ap_start = (uint32_t)ap_start; 233 params16->gdt = (uint32_t)gd->arch.gdt; 234 params16->gdt_limit = X86_GDT_SIZE - 1; 235 debug("gdt = %x, gdt_limit = %x\n", params16->gdt, params16->gdt_limit); 236 237 params = (struct sipi_params *)sipi_params; 238 debug("SIPI 32-bit params at %p\n", params); 239 params->idt_ptr = (uint32_t)x86_get_idt(); 240 241 params->stack_size = CONFIG_AP_STACK_SIZE; 242 size = params->stack_size * CONFIG_MAX_CPUS; 243 stack = memalign(size, 4096); 244 if (!stack) 245 return -ENOMEM; 246 params->stack_top = (u32)(stack + size); 247 248 params->microcode_ptr = 0; 249 params->msr_table_ptr = (u32)msr_save; 250 ret = save_bsp_msrs(msr_save, sizeof(msr_save)); 251 if (ret < 0) 252 return ret; 253 params->msr_count = ret; 254 255 params->c_handler = (uint32_t)&ap_init; 256 257 *ap_countp = ¶ms->ap_count; 258 atomic_set(*ap_countp, 0); 259 debug("SIPI vector is ready\n"); 260 261 return 0; 262 } 263 264 static int check_cpu_devices(int expected_cpus) 265 { 266 int i; 267 268 for (i = 0; i < expected_cpus; i++) { 269 struct udevice *dev; 270 int ret; 271 272 ret = uclass_find_device(UCLASS_CPU, i, &dev); 273 if (ret) { 274 debug("Cannot find CPU %d in device tree\n", i); 275 return ret; 276 } 277 } 278 279 return 0; 280 } 281 282 /* Returns 1 for timeout. 0 on success */ 283 static int apic_wait_timeout(int total_delay, int delay_step) 284 { 285 int total = 0; 286 int timeout = 0; 287 288 while (lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY) { 289 udelay(delay_step); 290 total += delay_step; 291 if (total >= total_delay) { 292 timeout = 1; 293 break; 294 } 295 } 296 297 return timeout; 298 } 299 300 static int start_aps(int ap_count, atomic_t *num_aps) 301 { 302 int sipi_vector; 303 /* Max location is 4KiB below 1MiB */ 304 const int max_vector_loc = ((1 << 20) - (1 << 12)) >> 12; 305 306 if (ap_count == 0) 307 return 0; 308 309 /* The vector is sent as a 4k aligned address in one byte */ 310 sipi_vector = AP_DEFAULT_BASE >> 12; 311 312 if (sipi_vector > max_vector_loc) { 313 printf("SIPI vector too large! 0x%08x\n", 314 sipi_vector); 315 return -1; 316 } 317 318 debug("Attempting to start %d APs\n", ap_count); 319 320 if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) { 321 debug("Waiting for ICR not to be busy..."); 322 if (apic_wait_timeout(1000, 50)) { 323 debug("timed out. Aborting.\n"); 324 return -1; 325 } else { 326 debug("done.\n"); 327 } 328 } 329 330 /* Send INIT IPI to all but self */ 331 lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0)); 332 lapic_write(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | 333 LAPIC_DM_INIT); 334 debug("Waiting for 10ms after sending INIT.\n"); 335 mdelay(10); 336 337 /* Send 1st SIPI */ 338 if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) { 339 debug("Waiting for ICR not to be busy..."); 340 if (apic_wait_timeout(1000, 50)) { 341 debug("timed out. Aborting.\n"); 342 return -1; 343 } else { 344 debug("done.\n"); 345 } 346 } 347 348 lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0)); 349 lapic_write(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | 350 LAPIC_DM_STARTUP | sipi_vector); 351 debug("Waiting for 1st SIPI to complete..."); 352 if (apic_wait_timeout(10000, 50)) { 353 debug("timed out.\n"); 354 return -1; 355 } else { 356 debug("done.\n"); 357 } 358 359 /* Wait for CPUs to check in up to 200 us */ 360 wait_for_aps(num_aps, ap_count, 200, 15); 361 362 /* Send 2nd SIPI */ 363 if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) { 364 debug("Waiting for ICR not to be busy..."); 365 if (apic_wait_timeout(1000, 50)) { 366 debug("timed out. Aborting.\n"); 367 return -1; 368 } else { 369 debug("done.\n"); 370 } 371 } 372 373 lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0)); 374 lapic_write(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | 375 LAPIC_DM_STARTUP | sipi_vector); 376 debug("Waiting for 2nd SIPI to complete..."); 377 if (apic_wait_timeout(10000, 50)) { 378 debug("timed out.\n"); 379 return -1; 380 } else { 381 debug("done.\n"); 382 } 383 384 /* Wait for CPUs to check in */ 385 if (wait_for_aps(num_aps, ap_count, 10000, 50)) { 386 debug("Not all APs checked in: %d/%d.\n", 387 atomic_read(num_aps), ap_count); 388 return -1; 389 } 390 391 return 0; 392 } 393 394 static int bsp_do_flight_plan(struct udevice *cpu, struct mp_params *mp_params) 395 { 396 int i; 397 int ret = 0; 398 const int timeout_us = 100000; 399 const int step_us = 100; 400 int num_aps = num_cpus - 1; 401 402 for (i = 0; i < mp_params->num_records; i++) { 403 struct mp_flight_record *rec = &mp_params->flight_plan[i]; 404 405 /* Wait for APs if the record is not released */ 406 if (atomic_read(&rec->barrier) == 0) { 407 /* Wait for the APs to check in */ 408 if (wait_for_aps(&rec->cpus_entered, num_aps, 409 timeout_us, step_us)) { 410 debug("MP record %d timeout.\n", i); 411 ret = -1; 412 } 413 } 414 415 if (rec->bsp_call != NULL) 416 rec->bsp_call(cpu, rec->bsp_arg); 417 418 release_barrier(&rec->barrier); 419 } 420 return ret; 421 } 422 423 static int init_bsp(struct udevice **devp) 424 { 425 char processor_name[CPU_MAX_NAME_LEN]; 426 int apic_id; 427 int ret; 428 429 cpu_get_name(processor_name); 430 debug("CPU: %s.\n", processor_name); 431 432 lapic_setup(); 433 434 apic_id = lapicid(); 435 ret = find_cpu_by_apid_id(apic_id, devp); 436 if (ret) { 437 printf("Cannot find boot CPU, APIC ID %d\n", apic_id); 438 return ret; 439 } 440 441 return 0; 442 } 443 444 int mp_init(struct mp_params *p) 445 { 446 int num_aps; 447 atomic_t *ap_count; 448 struct udevice *cpu; 449 int ret; 450 451 /* This will cause the CPUs devices to be bound */ 452 struct uclass *uc; 453 ret = uclass_get(UCLASS_CPU, &uc); 454 if (ret) 455 return ret; 456 457 ret = init_bsp(&cpu); 458 if (ret) { 459 debug("Cannot init boot CPU: err=%d\n", ret); 460 return ret; 461 } 462 463 if (p == NULL || p->flight_plan == NULL || p->num_records < 1) { 464 printf("Invalid MP parameters\n"); 465 return -1; 466 } 467 468 num_cpus = cpu_get_count(cpu); 469 if (num_cpus < 0) { 470 debug("Cannot get number of CPUs: err=%d\n", num_cpus); 471 return num_cpus; 472 } 473 474 if (num_cpus < 2) 475 debug("Warning: Only 1 CPU is detected\n"); 476 477 ret = check_cpu_devices(num_cpus); 478 if (ret) 479 debug("Warning: Device tree does not describe all CPUs. Extra ones will not be started correctly\n"); 480 481 /* Copy needed parameters so that APs have a reference to the plan */ 482 mp_info.num_records = p->num_records; 483 mp_info.records = p->flight_plan; 484 485 /* Load the SIPI vector */ 486 ret = load_sipi_vector(&ap_count); 487 if (ap_count == NULL) 488 return -1; 489 490 /* 491 * Make sure SIPI data hits RAM so the APs that come up will see 492 * the startup code even if the caches are disabled 493 */ 494 wbinvd(); 495 496 /* Start the APs providing number of APs and the cpus_entered field */ 497 num_aps = num_cpus - 1; 498 ret = start_aps(num_aps, ap_count); 499 if (ret) { 500 mdelay(1000); 501 debug("%d/%d eventually checked in?\n", atomic_read(ap_count), 502 num_aps); 503 return ret; 504 } 505 506 /* Walk the flight plan for the BSP */ 507 ret = bsp_do_flight_plan(cpu, p); 508 if (ret) { 509 debug("CPU init failed: err=%d\n", ret); 510 return ret; 511 } 512 513 return 0; 514 } 515 516 int mp_init_cpu(struct udevice *cpu, void *unused) 517 { 518 /* 519 * Multiple APs are brought up simultaneously and they may get the same 520 * seq num in the uclass_resolve_seq() during device_probe(). To avoid 521 * this, set req_seq to the reg number in the device tree in advance. 522 */ 523 cpu->req_seq = fdtdec_get_int(gd->fdt_blob, cpu->of_offset, "reg", -1); 524 525 return device_probe(cpu); 526 } 527