1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2011 The Chromium OS Authors. 4 * (C) Copyright 2010,2011 5 * Graeme Russ, <graeme.russ@gmail.com> 6 * 7 * Portions from Coreboot mainboard/google/link/romstage.c 8 * Copyright (C) 2007-2010 coresystems GmbH 9 * Copyright (C) 2011 Google Inc. 10 */ 11 12 #include <common.h> 13 #include <errno.h> 14 #include <fdtdec.h> 15 #include <malloc.h> 16 #include <net.h> 17 #include <rtc.h> 18 #include <spi.h> 19 #include <spi_flash.h> 20 #include <syscon.h> 21 #include <sysreset.h> 22 #include <asm/cpu.h> 23 #include <asm/processor.h> 24 #include <asm/gpio.h> 25 #include <asm/global_data.h> 26 #include <asm/intel_regs.h> 27 #include <asm/mrccache.h> 28 #include <asm/mrc_common.h> 29 #include <asm/mtrr.h> 30 #include <asm/pci.h> 31 #include <asm/report_platform.h> 32 #include <asm/arch/me.h> 33 #include <asm/arch/pei_data.h> 34 #include <asm/arch/pch.h> 35 #include <asm/post.h> 36 #include <asm/arch/sandybridge.h> 37 38 DECLARE_GLOBAL_DATA_PTR; 39 40 #define CMOS_OFFSET_MRC_SEED 152 41 #define CMOS_OFFSET_MRC_SEED_S3 156 42 #define CMOS_OFFSET_MRC_SEED_CHK 160 43 44 ulong board_get_usable_ram_top(ulong total_size) 45 { 46 return mrc_common_board_get_usable_ram_top(total_size); 47 } 48 49 int dram_init_banksize(void) 50 { 51 mrc_common_dram_init_banksize(); 52 53 return 0; 54 } 55 56 static int read_seed_from_cmos(struct pei_data *pei_data) 57 { 58 u16 c1, c2, checksum, seed_checksum; 59 struct udevice *dev; 60 int ret = 0; 61 62 ret = uclass_get_device(UCLASS_RTC, 0, &dev); 63 if (ret) { 64 debug("Cannot find RTC: err=%d\n", ret); 65 return -ENODEV; 66 } 67 68 /* 69 * Read scrambler seeds from CMOS RAM. We don't want to store them in 70 * SPI flash since they change on every boot and that would wear down 71 * the flash too much. So we store these in CMOS and the large MRC 72 * data in SPI flash. 73 */ 74 ret = rtc_read32(dev, CMOS_OFFSET_MRC_SEED, &pei_data->scrambler_seed); 75 if (!ret) { 76 ret = rtc_read32(dev, CMOS_OFFSET_MRC_SEED_S3, 77 &pei_data->scrambler_seed_s3); 78 } 79 if (ret) { 80 debug("Failed to read from RTC %s\n", dev->name); 81 return ret; 82 } 83 84 debug("Read scrambler seed 0x%08x from CMOS 0x%02x\n", 85 pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); 86 debug("Read S3 scrambler seed 0x%08x from CMOS 0x%02x\n", 87 pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); 88 89 /* Compute seed checksum and compare */ 90 c1 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed, 91 sizeof(u32)); 92 c2 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed_s3, 93 sizeof(u32)); 94 checksum = add_ip_checksums(sizeof(u32), c1, c2); 95 96 seed_checksum = rtc_read8(dev, CMOS_OFFSET_MRC_SEED_CHK); 97 seed_checksum |= rtc_read8(dev, CMOS_OFFSET_MRC_SEED_CHK + 1) << 8; 98 99 if (checksum != seed_checksum) { 100 debug("%s: invalid seed checksum\n", __func__); 101 pei_data->scrambler_seed = 0; 102 pei_data->scrambler_seed_s3 = 0; 103 return -EINVAL; 104 } 105 106 return 0; 107 } 108 109 static int prepare_mrc_cache(struct pei_data *pei_data) 110 { 111 struct mrc_data_container *mrc_cache; 112 struct mrc_region entry; 113 int ret; 114 115 ret = read_seed_from_cmos(pei_data); 116 if (ret) 117 return ret; 118 ret = mrccache_get_region(NULL, &entry); 119 if (ret) 120 return ret; 121 mrc_cache = mrccache_find_current(&entry); 122 if (!mrc_cache) 123 return -ENOENT; 124 125 pei_data->mrc_input = mrc_cache->data; 126 pei_data->mrc_input_len = mrc_cache->data_size; 127 debug("%s: at %p, size %x checksum %04x\n", __func__, 128 pei_data->mrc_input, pei_data->mrc_input_len, 129 mrc_cache->checksum); 130 131 return 0; 132 } 133 134 static int write_seeds_to_cmos(struct pei_data *pei_data) 135 { 136 u16 c1, c2, checksum; 137 struct udevice *dev; 138 int ret = 0; 139 140 ret = uclass_get_device(UCLASS_RTC, 0, &dev); 141 if (ret) { 142 debug("Cannot find RTC: err=%d\n", ret); 143 return -ENODEV; 144 } 145 146 /* Save the MRC seed values to CMOS */ 147 rtc_write32(dev, CMOS_OFFSET_MRC_SEED, pei_data->scrambler_seed); 148 debug("Save scrambler seed 0x%08x to CMOS 0x%02x\n", 149 pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); 150 151 rtc_write32(dev, CMOS_OFFSET_MRC_SEED_S3, pei_data->scrambler_seed_s3); 152 debug("Save s3 scrambler seed 0x%08x to CMOS 0x%02x\n", 153 pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); 154 155 /* Save a simple checksum of the seed values */ 156 c1 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed, 157 sizeof(u32)); 158 c2 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed_s3, 159 sizeof(u32)); 160 checksum = add_ip_checksums(sizeof(u32), c1, c2); 161 162 rtc_write8(dev, CMOS_OFFSET_MRC_SEED_CHK, checksum & 0xff); 163 rtc_write8(dev, CMOS_OFFSET_MRC_SEED_CHK + 1, (checksum >> 8) & 0xff); 164 165 return 0; 166 } 167 168 /* Use this hook to save our SDRAM parameters */ 169 int misc_init_r(void) 170 { 171 int ret; 172 173 ret = mrccache_save(); 174 if (ret) 175 printf("Unable to save MRC data: %d\n", ret); 176 177 return 0; 178 } 179 180 static void post_system_agent_init(struct udevice *dev, struct udevice *me_dev, 181 struct pei_data *pei_data) 182 { 183 uint16_t done; 184 185 /* 186 * Send ME init done for SandyBridge here. This is done inside the 187 * SystemAgent binary on IvyBridge 188 */ 189 dm_pci_read_config16(dev, PCI_DEVICE_ID, &done); 190 done &= BASE_REV_MASK; 191 if (BASE_REV_SNB == done) 192 intel_early_me_init_done(dev, me_dev, ME_INIT_STATUS_SUCCESS); 193 else 194 intel_me_status(me_dev); 195 196 /* If PCIe init is skipped, set the PEG clock gating */ 197 if (!pei_data->pcie_init) 198 setbits_le32(MCHBAR_REG(0x7010), 1); 199 } 200 201 static int recovery_mode_enabled(void) 202 { 203 return false; 204 } 205 206 static int copy_spd(struct udevice *dev, struct pei_data *peid) 207 { 208 const void *data; 209 int ret; 210 211 ret = mrc_locate_spd(dev, sizeof(peid->spd_data[0]), &data); 212 if (ret) { 213 debug("%s: Could not locate SPD (ret=%d)\n", __func__, ret); 214 return ret; 215 } 216 217 memcpy(peid->spd_data[0], data, sizeof(peid->spd_data[0])); 218 219 return 0; 220 } 221 222 /** 223 * sdram_find() - Find available memory 224 * 225 * This is a bit complicated since on x86 there are system memory holes all 226 * over the place. We create a list of available memory blocks 227 * 228 * @dev: Northbridge device 229 */ 230 static int sdram_find(struct udevice *dev) 231 { 232 struct memory_info *info = &gd->arch.meminfo; 233 uint32_t tseg_base, uma_size, tolud; 234 uint64_t tom, me_base, touud; 235 uint64_t uma_memory_base = 0; 236 unsigned long long tomk; 237 uint16_t ggc; 238 u32 val; 239 240 /* Total Memory 2GB example: 241 * 242 * 00000000 0000MB-1992MB 1992MB RAM (writeback) 243 * 7c800000 1992MB-2000MB 8MB TSEG (SMRR) 244 * 7d000000 2000MB-2002MB 2MB GFX GTT (uncached) 245 * 7d200000 2002MB-2034MB 32MB GFX UMA (uncached) 246 * 7f200000 2034MB TOLUD 247 * 7f800000 2040MB MEBASE 248 * 7f800000 2040MB-2048MB 8MB ME UMA (uncached) 249 * 80000000 2048MB TOM 250 * 100000000 4096MB-4102MB 6MB RAM (writeback) 251 * 252 * Total Memory 4GB example: 253 * 254 * 00000000 0000MB-2768MB 2768MB RAM (writeback) 255 * ad000000 2768MB-2776MB 8MB TSEG (SMRR) 256 * ad800000 2776MB-2778MB 2MB GFX GTT (uncached) 257 * ada00000 2778MB-2810MB 32MB GFX UMA (uncached) 258 * afa00000 2810MB TOLUD 259 * ff800000 4088MB MEBASE 260 * ff800000 4088MB-4096MB 8MB ME UMA (uncached) 261 * 100000000 4096MB TOM 262 * 100000000 4096MB-5374MB 1278MB RAM (writeback) 263 * 14fe00000 5368MB TOUUD 264 */ 265 266 /* Top of Upper Usable DRAM, including remap */ 267 dm_pci_read_config32(dev, TOUUD + 4, &val); 268 touud = (uint64_t)val << 32; 269 dm_pci_read_config32(dev, TOUUD, &val); 270 touud |= val; 271 272 /* Top of Lower Usable DRAM */ 273 dm_pci_read_config32(dev, TOLUD, &tolud); 274 275 /* Top of Memory - does not account for any UMA */ 276 dm_pci_read_config32(dev, 0xa4, &val); 277 tom = (uint64_t)val << 32; 278 dm_pci_read_config32(dev, 0xa0, &val); 279 tom |= val; 280 281 debug("TOUUD %llx TOLUD %08x TOM %llx\n", touud, tolud, tom); 282 283 /* ME UMA needs excluding if total memory <4GB */ 284 dm_pci_read_config32(dev, 0x74, &val); 285 me_base = (uint64_t)val << 32; 286 dm_pci_read_config32(dev, 0x70, &val); 287 me_base |= val; 288 289 debug("MEBASE %llx\n", me_base); 290 291 /* TODO: Get rid of all this shifting by 10 bits */ 292 tomk = tolud >> 10; 293 if (me_base == tolud) { 294 /* ME is from MEBASE-TOM */ 295 uma_size = (tom - me_base) >> 10; 296 /* Increment TOLUD to account for ME as RAM */ 297 tolud += uma_size << 10; 298 /* UMA starts at old TOLUD */ 299 uma_memory_base = tomk * 1024ULL; 300 debug("ME UMA base %llx size %uM\n", me_base, uma_size >> 10); 301 } 302 303 /* Graphics memory comes next */ 304 dm_pci_read_config16(dev, GGC, &ggc); 305 if (!(ggc & 2)) { 306 debug("IGD decoded, subtracting "); 307 308 /* Graphics memory */ 309 uma_size = ((ggc >> 3) & 0x1f) * 32 * 1024ULL; 310 debug("%uM UMA", uma_size >> 10); 311 tomk -= uma_size; 312 uma_memory_base = tomk * 1024ULL; 313 314 /* GTT Graphics Stolen Memory Size (GGMS) */ 315 uma_size = ((ggc >> 8) & 0x3) * 1024ULL; 316 tomk -= uma_size; 317 uma_memory_base = tomk * 1024ULL; 318 debug(" and %uM GTT\n", uma_size >> 10); 319 } 320 321 /* Calculate TSEG size from its base which must be below GTT */ 322 dm_pci_read_config32(dev, 0xb8, &tseg_base); 323 uma_size = (uma_memory_base - tseg_base) >> 10; 324 tomk -= uma_size; 325 uma_memory_base = tomk * 1024ULL; 326 debug("TSEG base 0x%08x size %uM\n", tseg_base, uma_size >> 10); 327 328 debug("Available memory below 4GB: %lluM\n", tomk >> 10); 329 330 /* Report the memory regions */ 331 mrc_add_memory_area(info, 1 << 20, 2 << 28); 332 mrc_add_memory_area(info, (2 << 28) + (2 << 20), 4 << 28); 333 mrc_add_memory_area(info, (4 << 28) + (2 << 20), tseg_base); 334 mrc_add_memory_area(info, 1ULL << 32, touud); 335 336 /* Add MTRRs for memory */ 337 mtrr_add_request(MTRR_TYPE_WRBACK, 0, 2ULL << 30); 338 mtrr_add_request(MTRR_TYPE_WRBACK, 2ULL << 30, 512 << 20); 339 mtrr_add_request(MTRR_TYPE_WRBACK, 0xaULL << 28, 256 << 20); 340 mtrr_add_request(MTRR_TYPE_UNCACHEABLE, tseg_base, 16 << 20); 341 mtrr_add_request(MTRR_TYPE_UNCACHEABLE, tseg_base + (16 << 20), 342 32 << 20); 343 344 /* 345 * If >= 4GB installed then memory from TOLUD to 4GB 346 * is remapped above TOM, TOUUD will account for both 347 */ 348 if (touud > (1ULL << 32ULL)) { 349 debug("Available memory above 4GB: %lluM\n", 350 (touud >> 20) - 4096); 351 } 352 353 return 0; 354 } 355 356 static void rcba_config(void) 357 { 358 /* 359 * GFX INTA -> PIRQA (MSI) 360 * D28IP_P3IP WLAN INTA -> PIRQB 361 * D29IP_E1P EHCI1 INTA -> PIRQD 362 * D26IP_E2P EHCI2 INTA -> PIRQF 363 * D31IP_SIP SATA INTA -> PIRQF (MSI) 364 * D31IP_SMIP SMBUS INTB -> PIRQH 365 * D31IP_TTIP THRT INTC -> PIRQA 366 * D27IP_ZIP HDA INTA -> PIRQA (MSI) 367 * 368 * TRACKPAD -> PIRQE (Edge Triggered) 369 * TOUCHSCREEN -> PIRQG (Edge Triggered) 370 */ 371 372 /* Device interrupt pin register (board specific) */ 373 writel((INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | 374 (INTB << D31IP_SMIP) | (INTA << D31IP_SIP), RCB_REG(D31IP)); 375 writel(NOINT << D30IP_PIP, RCB_REG(D30IP)); 376 writel(INTA << D29IP_E1P, RCB_REG(D29IP)); 377 writel(INTA << D28IP_P3IP, RCB_REG(D28IP)); 378 writel(INTA << D27IP_ZIP, RCB_REG(D27IP)); 379 writel(INTA << D26IP_E2P, RCB_REG(D26IP)); 380 writel(NOINT << D25IP_LIP, RCB_REG(D25IP)); 381 writel(NOINT << D22IP_MEI1IP, RCB_REG(D22IP)); 382 383 /* Device interrupt route registers */ 384 writel(DIR_ROUTE(PIRQB, PIRQH, PIRQA, PIRQC), RCB_REG(D31IR)); 385 writel(DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG), RCB_REG(D29IR)); 386 writel(DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE), RCB_REG(D28IR)); 387 writel(DIR_ROUTE(PIRQA, PIRQH, PIRQA, PIRQB), RCB_REG(D27IR)); 388 writel(DIR_ROUTE(PIRQF, PIRQE, PIRQG, PIRQH), RCB_REG(D26IR)); 389 writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D25IR)); 390 writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D22IR)); 391 392 /* Enable IOAPIC (generic) */ 393 writew(0x0100, RCB_REG(OIC)); 394 /* PCH BWG says to read back the IOAPIC enable register */ 395 (void)readw(RCB_REG(OIC)); 396 397 /* Disable unused devices (board specific) */ 398 setbits_le32(RCB_REG(FD), PCH_DISABLE_ALWAYS); 399 } 400 401 int dram_init(void) 402 { 403 struct pei_data _pei_data __aligned(8) = { 404 .pei_version = PEI_VERSION, 405 .mchbar = MCH_BASE_ADDRESS, 406 .dmibar = DEFAULT_DMIBAR, 407 .epbar = DEFAULT_EPBAR, 408 .pciexbar = CONFIG_PCIE_ECAM_BASE, 409 .smbusbar = SMBUS_IO_BASE, 410 .wdbbar = 0x4000000, 411 .wdbsize = 0x1000, 412 .hpet_address = CONFIG_HPET_ADDRESS, 413 .rcba = DEFAULT_RCBABASE, 414 .pmbase = DEFAULT_PMBASE, 415 .gpiobase = DEFAULT_GPIOBASE, 416 .thermalbase = 0xfed08000, 417 .system_type = 0, /* 0 Mobile, 1 Desktop/Server */ 418 .tseg_size = CONFIG_SMM_TSEG_SIZE, 419 .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, 420 .ec_present = 1, 421 .ddr3lv_support = 1, 422 /* 423 * 0 = leave channel enabled 424 * 1 = disable dimm 0 on channel 425 * 2 = disable dimm 1 on channel 426 * 3 = disable dimm 0+1 on channel 427 */ 428 .dimm_channel0_disabled = 2, 429 .dimm_channel1_disabled = 2, 430 .max_ddr3_freq = 1600, 431 .usb_port_config = { 432 /* 433 * Empty and onboard Ports 0-7, set to un-used pin 434 * OC3 435 */ 436 { 0, 3, 0x0000 }, /* P0= Empty */ 437 { 1, 0, 0x0040 }, /* P1= Left USB 1 (OC0) */ 438 { 1, 1, 0x0040 }, /* P2= Left USB 2 (OC1) */ 439 { 1, 3, 0x0040 }, /* P3= SDCARD (no OC) */ 440 { 0, 3, 0x0000 }, /* P4= Empty */ 441 { 1, 3, 0x0040 }, /* P5= WWAN (no OC) */ 442 { 0, 3, 0x0000 }, /* P6= Empty */ 443 { 0, 3, 0x0000 }, /* P7= Empty */ 444 /* 445 * Empty and onboard Ports 8-13, set to un-used pin 446 * OC4 447 */ 448 { 1, 4, 0x0040 }, /* P8= Camera (no OC) */ 449 { 1, 4, 0x0040 }, /* P9= Bluetooth (no OC) */ 450 { 0, 4, 0x0000 }, /* P10= Empty */ 451 { 0, 4, 0x0000 }, /* P11= Empty */ 452 { 0, 4, 0x0000 }, /* P12= Empty */ 453 { 0, 4, 0x0000 }, /* P13= Empty */ 454 }, 455 }; 456 struct pei_data *pei_data = &_pei_data; 457 struct udevice *dev, *me_dev; 458 int ret; 459 460 /* We need the pinctrl set up early */ 461 ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev); 462 if (ret) { 463 debug("%s: Could not get pinconf (ret=%d)\n", __func__, ret); 464 return ret; 465 } 466 467 ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &dev); 468 if (ret) { 469 debug("%s: Could not get northbridge (ret=%d)\n", __func__, 470 ret); 471 return ret; 472 } 473 ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev); 474 if (ret) { 475 debug("%s: Could not get ME (ret=%d)\n", __func__, ret); 476 return ret; 477 } 478 ret = copy_spd(dev, pei_data); 479 if (ret) { 480 debug("%s: Could not get SPD (ret=%d)\n", __func__, ret); 481 return ret; 482 } 483 pei_data->boot_mode = gd->arch.pei_boot_mode; 484 debug("Boot mode %d\n", gd->arch.pei_boot_mode); 485 debug("mrc_input %p\n", pei_data->mrc_input); 486 487 /* 488 * Do not pass MRC data in for recovery mode boot, 489 * Always pass it in for S3 resume. 490 */ 491 if (!recovery_mode_enabled() || 492 pei_data->boot_mode == PEI_BOOT_RESUME) { 493 ret = prepare_mrc_cache(pei_data); 494 if (ret) 495 debug("prepare_mrc_cache failed: %d\n", ret); 496 } 497 498 /* If MRC data is not found we cannot continue S3 resume. */ 499 if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) { 500 debug("Giving up in sdram_initialize: No MRC data\n"); 501 sysreset_walk_halt(SYSRESET_COLD); 502 } 503 504 /* Pass console handler in pei_data */ 505 pei_data->tx_byte = sdram_console_tx_byte; 506 507 /* Wait for ME to be ready */ 508 ret = intel_early_me_init(me_dev); 509 if (ret) { 510 debug("%s: Could not init ME (ret=%d)\n", __func__, ret); 511 return ret; 512 } 513 ret = intel_early_me_uma_size(me_dev); 514 if (ret < 0) { 515 debug("%s: Could not get UMA size (ret=%d)\n", __func__, ret); 516 return ret; 517 } 518 519 ret = mrc_common_init(dev, pei_data, false); 520 if (ret) { 521 debug("%s: mrc_common_init() failed (ret=%d)\n", __func__, ret); 522 return ret; 523 } 524 525 ret = sdram_find(dev); 526 if (ret) { 527 debug("%s: sdram_find() failed (ret=%d)\n", __func__, ret); 528 return ret; 529 } 530 gd->ram_size = gd->arch.meminfo.total_32bit_memory; 531 532 debug("MRC output data length %#x at %p\n", pei_data->mrc_output_len, 533 pei_data->mrc_output); 534 535 post_system_agent_init(dev, me_dev, pei_data); 536 report_memory_config(); 537 538 /* S3 resume: don't save scrambler seed or MRC data */ 539 if (pei_data->boot_mode != PEI_BOOT_RESUME) { 540 /* 541 * This will be copied to SDRAM in reserve_arch(), then written 542 * to SPI flash in mrccache_save() 543 */ 544 gd->arch.mrc_output = (char *)pei_data->mrc_output; 545 gd->arch.mrc_output_len = pei_data->mrc_output_len; 546 ret = write_seeds_to_cmos(pei_data); 547 if (ret) 548 debug("Failed to write seeds to CMOS: %d\n", ret); 549 } 550 551 writew(0xCAFE, MCHBAR_REG(SSKPD)); 552 if (ret) 553 return ret; 554 555 rcba_config(); 556 557 return 0; 558 } 559