1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * (C) Copyright 2010,2011 4 * Graeme Russ, <graeme.russ@gmail.com> 5 * 6 * Portions from Coreboot mainboard/google/link/romstage.c 7 * Copyright (C) 2007-2010 coresystems GmbH 8 * Copyright (C) 2011 Google Inc. 9 * 10 * SPDX-License-Identifier: GPL-2.0 11 */ 12 13 #include <common.h> 14 #include <errno.h> 15 #include <fdtdec.h> 16 #include <malloc.h> 17 #include <asm/processor.h> 18 #include <asm/gpio.h> 19 #include <asm/global_data.h> 20 #include <asm/mtrr.h> 21 #include <asm/pci.h> 22 #include <asm/arch/me.h> 23 #include <asm/arch/pei_data.h> 24 #include <asm/arch/pch.h> 25 #include <asm/post.h> 26 #include <asm/arch/sandybridge.h> 27 28 DECLARE_GLOBAL_DATA_PTR; 29 30 /* 31 * This function looks for the highest region of memory lower than 4GB which 32 * has enough space for U-Boot where U-Boot is aligned on a page boundary. 33 * It overrides the default implementation found elsewhere which simply 34 * picks the end of ram, wherever that may be. The location of the stack, 35 * the relocation address, and how far U-Boot is moved by relocation are 36 * set in the global data structure. 37 */ 38 ulong board_get_usable_ram_top(ulong total_size) 39 { 40 struct memory_info *info = &gd->arch.meminfo; 41 uintptr_t dest_addr = 0; 42 struct memory_area *largest = NULL; 43 int i; 44 45 /* Find largest area of memory below 4GB */ 46 47 for (i = 0; i < info->num_areas; i++) { 48 struct memory_area *area = &info->area[i]; 49 50 if (area->start >= 1ULL << 32) 51 continue; 52 if (!largest || area->size > largest->size) 53 largest = area; 54 } 55 56 /* If no suitable area was found, return an error. */ 57 assert(largest); 58 if (!largest || largest->size < (2 << 20)) 59 panic("No available memory found for relocation"); 60 61 dest_addr = largest->start + largest->size; 62 63 return (ulong)dest_addr; 64 } 65 66 void dram_init_banksize(void) 67 { 68 struct memory_info *info = &gd->arch.meminfo; 69 int num_banks; 70 int i; 71 72 for (i = 0, num_banks = 0; i < info->num_areas; i++) { 73 struct memory_area *area = &info->area[i]; 74 75 if (area->start >= 1ULL << 32) 76 continue; 77 gd->bd->bi_dram[num_banks].start = area->start; 78 gd->bd->bi_dram[num_banks].size = area->size; 79 num_banks++; 80 } 81 } 82 83 static const char *const ecc_decoder[] = { 84 "inactive", 85 "active on IO", 86 "disabled on IO", 87 "active" 88 }; 89 90 /* 91 * Dump in the log memory controller configuration as read from the memory 92 * controller registers. 93 */ 94 static void report_memory_config(void) 95 { 96 u32 addr_decoder_common, addr_decode_ch[2]; 97 int i; 98 99 addr_decoder_common = readl(MCHBAR_REG(0x5000)); 100 addr_decode_ch[0] = readl(MCHBAR_REG(0x5004)); 101 addr_decode_ch[1] = readl(MCHBAR_REG(0x5008)); 102 103 debug("memcfg DDR3 clock %d MHz\n", 104 (readl(MCHBAR_REG(0x5e04)) * 13333 * 2 + 50) / 100); 105 debug("memcfg channel assignment: A: %d, B % d, C % d\n", 106 addr_decoder_common & 3, 107 (addr_decoder_common >> 2) & 3, 108 (addr_decoder_common >> 4) & 3); 109 110 for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { 111 u32 ch_conf = addr_decode_ch[i]; 112 debug("memcfg channel[%d] config (%8.8x):\n", i, ch_conf); 113 debug(" ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]); 114 debug(" enhanced interleave mode %s\n", 115 ((ch_conf >> 22) & 1) ? "on" : "off"); 116 debug(" rank interleave %s\n", 117 ((ch_conf >> 21) & 1) ? "on" : "off"); 118 debug(" DIMMA %d MB width x%d %s rank%s\n", 119 ((ch_conf >> 0) & 0xff) * 256, 120 ((ch_conf >> 19) & 1) ? 16 : 8, 121 ((ch_conf >> 17) & 1) ? "dual" : "single", 122 ((ch_conf >> 16) & 1) ? "" : ", selected"); 123 debug(" DIMMB %d MB width x%d %s rank%s\n", 124 ((ch_conf >> 8) & 0xff) * 256, 125 ((ch_conf >> 20) & 1) ? 16 : 8, 126 ((ch_conf >> 18) & 1) ? "dual" : "single", 127 ((ch_conf >> 16) & 1) ? ", selected" : ""); 128 } 129 } 130 131 static void post_system_agent_init(struct pei_data *pei_data) 132 { 133 /* If PCIe init is skipped, set the PEG clock gating */ 134 if (!pei_data->pcie_init) 135 setbits_le32(MCHBAR_REG(0x7010), 1); 136 } 137 138 static asmlinkage void console_tx_byte(unsigned char byte) 139 { 140 #ifdef DEBUG 141 putc(byte); 142 #endif 143 } 144 145 /** 146 * Find the PEI executable in the ROM and execute it. 147 * 148 * @param pei_data: configuration data for UEFI PEI reference code 149 */ 150 int sdram_initialise(struct pei_data *pei_data) 151 { 152 unsigned version; 153 const char *data; 154 uint16_t done; 155 int ret; 156 157 report_platform_info(); 158 159 /* Wait for ME to be ready */ 160 ret = intel_early_me_init(); 161 if (ret) 162 return ret; 163 ret = intel_early_me_uma_size(); 164 if (ret < 0) 165 return ret; 166 167 debug("Starting UEFI PEI System Agent\n"); 168 169 /* If MRC data is not found we cannot continue S3 resume. */ 170 if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) { 171 debug("Giving up in sdram_initialize: No MRC data\n"); 172 outb(0x6, PORT_RESET); 173 cpu_hlt(); 174 } 175 176 /* Pass console handler in pei_data */ 177 pei_data->tx_byte = console_tx_byte; 178 179 debug("PEI data at %p, size %x:\n", pei_data, sizeof(*pei_data)); 180 181 data = (char *)CONFIG_X86_MRC_ADDR; 182 if (data) { 183 int rv; 184 int (*func)(struct pei_data *); 185 186 debug("Calling MRC at %p\n", data); 187 post_code(POST_PRE_MRC); 188 func = (int (*)(struct pei_data *))data; 189 rv = func(pei_data); 190 post_code(POST_MRC); 191 if (rv) { 192 switch (rv) { 193 case -1: 194 printf("PEI version mismatch.\n"); 195 break; 196 case -2: 197 printf("Invalid memory frequency.\n"); 198 break; 199 default: 200 printf("MRC returned %x.\n", rv); 201 } 202 printf("Nonzero MRC return value.\n"); 203 return -EFAULT; 204 } 205 } else { 206 printf("UEFI PEI System Agent not found.\n"); 207 return -ENOSYS; 208 } 209 210 #if CONFIG_USBDEBUG 211 /* mrc.bin reconfigures USB, so reinit it to have debug */ 212 early_usbdebug_init(); 213 #endif 214 215 version = readl(MCHBAR_REG(0x5034)); 216 debug("System Agent Version %d.%d.%d Build %d\n", 217 version >> 24 , (version >> 16) & 0xff, 218 (version >> 8) & 0xff, version & 0xff); 219 220 /* 221 * Send ME init done for SandyBridge here. This is done inside the 222 * SystemAgent binary on IvyBridge 223 */ 224 done = pci_read_config32(PCH_DEV, PCI_DEVICE_ID); 225 done &= BASE_REV_MASK; 226 if (BASE_REV_SNB == done) 227 intel_early_me_init_done(ME_INIT_STATUS_SUCCESS); 228 else 229 intel_early_me_status(); 230 231 post_system_agent_init(pei_data); 232 report_memory_config(); 233 234 return 0; 235 } 236 237 static int copy_spd(struct pei_data *peid) 238 { 239 const int gpio_vector[] = {41, 42, 43, 10, -1}; 240 int spd_index; 241 const void *blob = gd->fdt_blob; 242 int node, spd_node; 243 int ret, i; 244 245 for (i = 0; ; i++) { 246 if (gpio_vector[i] == -1) 247 break; 248 ret = gpio_requestf(gpio_vector[i], "spd_id%d", i); 249 if (ret) { 250 debug("%s: Could not request gpio %d\n", __func__, 251 gpio_vector[i]); 252 return ret; 253 } 254 } 255 spd_index = gpio_get_values_as_int(gpio_vector); 256 debug("spd index %d\n", spd_index); 257 node = fdtdec_next_compatible(blob, 0, COMPAT_MEMORY_SPD); 258 if (node < 0) { 259 printf("SPD data not found.\n"); 260 return -ENOENT; 261 } 262 263 for (spd_node = fdt_first_subnode(blob, node); 264 spd_node > 0; 265 spd_node = fdt_next_subnode(blob, spd_node)) { 266 const char *data; 267 int len; 268 269 if (fdtdec_get_int(blob, spd_node, "reg", -1) != spd_index) 270 continue; 271 data = fdt_getprop(blob, spd_node, "data", &len); 272 if (len < sizeof(peid->spd_data[0])) { 273 printf("Missing SPD data\n"); 274 return -EINVAL; 275 } 276 277 debug("Using SDRAM SPD data for '%s'\n", 278 fdt_get_name(blob, spd_node, NULL)); 279 memcpy(peid->spd_data[0], data, sizeof(peid->spd_data[0])); 280 break; 281 } 282 283 if (spd_node < 0) { 284 printf("No SPD data found for index %d\n", spd_index); 285 return -ENOENT; 286 } 287 288 return 0; 289 } 290 291 /** 292 * add_memory_area() - Add a new usable memory area to our list 293 * 294 * Note: @start and @end must not span the first 4GB boundary 295 * 296 * @info: Place to store memory info 297 * @start: Start of this memory area 298 * @end: End of this memory area + 1 299 */ 300 static int add_memory_area(struct memory_info *info, 301 uint64_t start, uint64_t end) 302 { 303 struct memory_area *ptr; 304 305 if (info->num_areas == CONFIG_NR_DRAM_BANKS) 306 return -ENOSPC; 307 308 ptr = &info->area[info->num_areas]; 309 ptr->start = start; 310 ptr->size = end - start; 311 info->total_memory += ptr->size; 312 if (ptr->start < (1ULL << 32)) 313 info->total_32bit_memory += ptr->size; 314 debug("%d: memory %llx size %llx, total now %llx / %llx\n", 315 info->num_areas, ptr->start, ptr->size, 316 info->total_32bit_memory, info->total_memory); 317 info->num_areas++; 318 319 return 0; 320 } 321 322 /** 323 * sdram_find() - Find available memory 324 * 325 * This is a bit complicated since on x86 there are system memory holes all 326 * over the place. We create a list of available memory blocks 327 */ 328 static int sdram_find(pci_dev_t dev) 329 { 330 struct memory_info *info = &gd->arch.meminfo; 331 uint32_t tseg_base, uma_size, tolud; 332 uint64_t tom, me_base, touud; 333 uint64_t uma_memory_base = 0; 334 uint64_t uma_memory_size; 335 unsigned long long tomk; 336 uint16_t ggc; 337 338 /* Total Memory 2GB example: 339 * 340 * 00000000 0000MB-1992MB 1992MB RAM (writeback) 341 * 7c800000 1992MB-2000MB 8MB TSEG (SMRR) 342 * 7d000000 2000MB-2002MB 2MB GFX GTT (uncached) 343 * 7d200000 2002MB-2034MB 32MB GFX UMA (uncached) 344 * 7f200000 2034MB TOLUD 345 * 7f800000 2040MB MEBASE 346 * 7f800000 2040MB-2048MB 8MB ME UMA (uncached) 347 * 80000000 2048MB TOM 348 * 100000000 4096MB-4102MB 6MB RAM (writeback) 349 * 350 * Total Memory 4GB example: 351 * 352 * 00000000 0000MB-2768MB 2768MB RAM (writeback) 353 * ad000000 2768MB-2776MB 8MB TSEG (SMRR) 354 * ad800000 2776MB-2778MB 2MB GFX GTT (uncached) 355 * ada00000 2778MB-2810MB 32MB GFX UMA (uncached) 356 * afa00000 2810MB TOLUD 357 * ff800000 4088MB MEBASE 358 * ff800000 4088MB-4096MB 8MB ME UMA (uncached) 359 * 100000000 4096MB TOM 360 * 100000000 4096MB-5374MB 1278MB RAM (writeback) 361 * 14fe00000 5368MB TOUUD 362 */ 363 364 /* Top of Upper Usable DRAM, including remap */ 365 touud = pci_read_config32(dev, TOUUD+4); 366 touud <<= 32; 367 touud |= pci_read_config32(dev, TOUUD); 368 369 /* Top of Lower Usable DRAM */ 370 tolud = pci_read_config32(dev, TOLUD); 371 372 /* Top of Memory - does not account for any UMA */ 373 tom = pci_read_config32(dev, 0xa4); 374 tom <<= 32; 375 tom |= pci_read_config32(dev, 0xa0); 376 377 debug("TOUUD %llx TOLUD %08x TOM %llx\n", touud, tolud, tom); 378 379 /* ME UMA needs excluding if total memory <4GB */ 380 me_base = pci_read_config32(dev, 0x74); 381 me_base <<= 32; 382 me_base |= pci_read_config32(dev, 0x70); 383 384 debug("MEBASE %llx\n", me_base); 385 386 /* TODO: Get rid of all this shifting by 10 bits */ 387 tomk = tolud >> 10; 388 if (me_base == tolud) { 389 /* ME is from MEBASE-TOM */ 390 uma_size = (tom - me_base) >> 10; 391 /* Increment TOLUD to account for ME as RAM */ 392 tolud += uma_size << 10; 393 /* UMA starts at old TOLUD */ 394 uma_memory_base = tomk * 1024ULL; 395 uma_memory_size = uma_size * 1024ULL; 396 debug("ME UMA base %llx size %uM\n", me_base, uma_size >> 10); 397 } 398 399 /* Graphics memory comes next */ 400 ggc = pci_read_config16(dev, GGC); 401 if (!(ggc & 2)) { 402 debug("IGD decoded, subtracting "); 403 404 /* Graphics memory */ 405 uma_size = ((ggc >> 3) & 0x1f) * 32 * 1024ULL; 406 debug("%uM UMA", uma_size >> 10); 407 tomk -= uma_size; 408 uma_memory_base = tomk * 1024ULL; 409 uma_memory_size += uma_size * 1024ULL; 410 411 /* GTT Graphics Stolen Memory Size (GGMS) */ 412 uma_size = ((ggc >> 8) & 0x3) * 1024ULL; 413 tomk -= uma_size; 414 uma_memory_base = tomk * 1024ULL; 415 uma_memory_size += uma_size * 1024ULL; 416 debug(" and %uM GTT\n", uma_size >> 10); 417 } 418 419 /* Calculate TSEG size from its base which must be below GTT */ 420 tseg_base = pci_read_config32(dev, 0xb8); 421 uma_size = (uma_memory_base - tseg_base) >> 10; 422 tomk -= uma_size; 423 uma_memory_base = tomk * 1024ULL; 424 uma_memory_size += uma_size * 1024ULL; 425 debug("TSEG base 0x%08x size %uM\n", tseg_base, uma_size >> 10); 426 427 debug("Available memory below 4GB: %lluM\n", tomk >> 10); 428 429 /* Report the memory regions */ 430 add_memory_area(info, 1 << 20, 2 << 28); 431 add_memory_area(info, (2 << 28) + (2 << 20), 4 << 28); 432 add_memory_area(info, (4 << 28) + (2 << 20), tseg_base); 433 add_memory_area(info, 1ULL << 32, touud); 434 435 /* Add MTRRs for memory */ 436 mtrr_add_request(MTRR_TYPE_WRBACK, 0, 2ULL << 30); 437 mtrr_add_request(MTRR_TYPE_WRBACK, 2ULL << 30, 512 << 20); 438 mtrr_add_request(MTRR_TYPE_WRBACK, 0xaULL << 28, 256 << 20); 439 mtrr_add_request(MTRR_TYPE_UNCACHEABLE, tseg_base, 16 << 20); 440 mtrr_add_request(MTRR_TYPE_UNCACHEABLE, tseg_base + (16 << 20), 441 32 << 20); 442 443 /* 444 * If >= 4GB installed then memory from TOLUD to 4GB 445 * is remapped above TOM, TOUUD will account for both 446 */ 447 if (touud > (1ULL << 32ULL)) { 448 debug("Available memory above 4GB: %lluM\n", 449 (touud >> 20) - 4096); 450 } 451 452 return 0; 453 } 454 455 static void rcba_config(void) 456 { 457 /* 458 * GFX INTA -> PIRQA (MSI) 459 * D28IP_P3IP WLAN INTA -> PIRQB 460 * D29IP_E1P EHCI1 INTA -> PIRQD 461 * D26IP_E2P EHCI2 INTA -> PIRQF 462 * D31IP_SIP SATA INTA -> PIRQF (MSI) 463 * D31IP_SMIP SMBUS INTB -> PIRQH 464 * D31IP_TTIP THRT INTC -> PIRQA 465 * D27IP_ZIP HDA INTA -> PIRQA (MSI) 466 * 467 * TRACKPAD -> PIRQE (Edge Triggered) 468 * TOUCHSCREEN -> PIRQG (Edge Triggered) 469 */ 470 471 /* Device interrupt pin register (board specific) */ 472 writel((INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | 473 (INTB << D31IP_SMIP) | (INTA << D31IP_SIP), RCB_REG(D31IP)); 474 writel(NOINT << D30IP_PIP, RCB_REG(D30IP)); 475 writel(INTA << D29IP_E1P, RCB_REG(D29IP)); 476 writel(INTA << D28IP_P3IP, RCB_REG(D28IP)); 477 writel(INTA << D27IP_ZIP, RCB_REG(D27IP)); 478 writel(INTA << D26IP_E2P, RCB_REG(D26IP)); 479 writel(NOINT << D25IP_LIP, RCB_REG(D25IP)); 480 writel(NOINT << D22IP_MEI1IP, RCB_REG(D22IP)); 481 482 /* Device interrupt route registers */ 483 writel(DIR_ROUTE(PIRQB, PIRQH, PIRQA, PIRQC), RCB_REG(D31IR)); 484 writel(DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG), RCB_REG(D29IR)); 485 writel(DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE), RCB_REG(D28IR)); 486 writel(DIR_ROUTE(PIRQA, PIRQH, PIRQA, PIRQB), RCB_REG(D27IR)); 487 writel(DIR_ROUTE(PIRQF, PIRQE, PIRQG, PIRQH), RCB_REG(D26IR)); 488 writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D25IR)); 489 writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D22IR)); 490 491 /* Enable IOAPIC (generic) */ 492 writew(0x0100, RCB_REG(OIC)); 493 /* PCH BWG says to read back the IOAPIC enable register */ 494 (void)readw(RCB_REG(OIC)); 495 496 /* Disable unused devices (board specific) */ 497 setbits_le32(RCB_REG(FD), PCH_DISABLE_ALWAYS); 498 } 499 500 int dram_init(void) 501 { 502 struct pei_data pei_data __aligned(8) = { 503 .pei_version = PEI_VERSION, 504 .mchbar = DEFAULT_MCHBAR, 505 .dmibar = DEFAULT_DMIBAR, 506 .epbar = DEFAULT_EPBAR, 507 .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, 508 .smbusbar = SMBUS_IO_BASE, 509 .wdbbar = 0x4000000, 510 .wdbsize = 0x1000, 511 .hpet_address = CONFIG_HPET_ADDRESS, 512 .rcba = DEFAULT_RCBABASE, 513 .pmbase = DEFAULT_PMBASE, 514 .gpiobase = DEFAULT_GPIOBASE, 515 .thermalbase = 0xfed08000, 516 .system_type = 0, /* 0 Mobile, 1 Desktop/Server */ 517 .tseg_size = CONFIG_SMM_TSEG_SIZE, 518 .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, 519 .ec_present = 1, 520 .ddr3lv_support = 1, 521 /* 522 * 0 = leave channel enabled 523 * 1 = disable dimm 0 on channel 524 * 2 = disable dimm 1 on channel 525 * 3 = disable dimm 0+1 on channel 526 */ 527 .dimm_channel0_disabled = 2, 528 .dimm_channel1_disabled = 2, 529 .max_ddr3_freq = 1600, 530 .usb_port_config = { 531 /* 532 * Empty and onboard Ports 0-7, set to un-used pin 533 * OC3 534 */ 535 { 0, 3, 0x0000 }, /* P0= Empty */ 536 { 1, 0, 0x0040 }, /* P1= Left USB 1 (OC0) */ 537 { 1, 1, 0x0040 }, /* P2= Left USB 2 (OC1) */ 538 { 1, 3, 0x0040 }, /* P3= SDCARD (no OC) */ 539 { 0, 3, 0x0000 }, /* P4= Empty */ 540 { 1, 3, 0x0040 }, /* P5= WWAN (no OC) */ 541 { 0, 3, 0x0000 }, /* P6= Empty */ 542 { 0, 3, 0x0000 }, /* P7= Empty */ 543 /* 544 * Empty and onboard Ports 8-13, set to un-used pin 545 * OC4 546 */ 547 { 1, 4, 0x0040 }, /* P8= Camera (no OC) */ 548 { 1, 4, 0x0040 }, /* P9= Bluetooth (no OC) */ 549 { 0, 4, 0x0000 }, /* P10= Empty */ 550 { 0, 4, 0x0000 }, /* P11= Empty */ 551 { 0, 4, 0x0000 }, /* P12= Empty */ 552 { 0, 4, 0x0000 }, /* P13= Empty */ 553 }, 554 }; 555 pci_dev_t dev = PCI_BDF(0, 0, 0); 556 int ret; 557 558 debug("Boot mode %d\n", gd->arch.pei_boot_mode); 559 debug("mcr_input %p\n", pei_data.mrc_input); 560 pei_data.boot_mode = gd->arch.pei_boot_mode; 561 ret = copy_spd(&pei_data); 562 if (!ret) 563 ret = sdram_initialise(&pei_data); 564 if (ret) 565 return ret; 566 567 rcba_config(); 568 quick_ram_check(); 569 570 writew(0xCAFE, MCHBAR_REG(SSKPD)); 571 572 post_code(POST_DRAM); 573 574 ret = sdram_find(dev); 575 if (ret) 576 return ret; 577 578 gd->ram_size = gd->arch.meminfo.total_32bit_memory; 579 580 return 0; 581 } 582