1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * (C) Copyright 2010,2011 4 * Graeme Russ, <graeme.russ@gmail.com> 5 * 6 * Portions from Coreboot mainboard/google/link/romstage.c 7 * Copyright (C) 2007-2010 coresystems GmbH 8 * Copyright (C) 2011 Google Inc. 9 * 10 * SPDX-License-Identifier: GPL-2.0 11 */ 12 13 #include <common.h> 14 #include <errno.h> 15 #include <fdtdec.h> 16 #include <malloc.h> 17 #include <net.h> 18 #include <rtc.h> 19 #include <spi.h> 20 #include <spi_flash.h> 21 #include <asm/processor.h> 22 #include <asm/gpio.h> 23 #include <asm/global_data.h> 24 #include <asm/mrccache.h> 25 #include <asm/mtrr.h> 26 #include <asm/pci.h> 27 #include <asm/arch/me.h> 28 #include <asm/arch/pei_data.h> 29 #include <asm/arch/pch.h> 30 #include <asm/post.h> 31 #include <asm/arch/sandybridge.h> 32 33 DECLARE_GLOBAL_DATA_PTR; 34 35 #define CMOS_OFFSET_MRC_SEED 152 36 #define CMOS_OFFSET_MRC_SEED_S3 156 37 #define CMOS_OFFSET_MRC_SEED_CHK 160 38 39 /* 40 * This function looks for the highest region of memory lower than 4GB which 41 * has enough space for U-Boot where U-Boot is aligned on a page boundary. 42 * It overrides the default implementation found elsewhere which simply 43 * picks the end of ram, wherever that may be. The location of the stack, 44 * the relocation address, and how far U-Boot is moved by relocation are 45 * set in the global data structure. 46 */ 47 ulong board_get_usable_ram_top(ulong total_size) 48 { 49 struct memory_info *info = &gd->arch.meminfo; 50 uintptr_t dest_addr = 0; 51 struct memory_area *largest = NULL; 52 int i; 53 54 /* Find largest area of memory below 4GB */ 55 56 for (i = 0; i < info->num_areas; i++) { 57 struct memory_area *area = &info->area[i]; 58 59 if (area->start >= 1ULL << 32) 60 continue; 61 if (!largest || area->size > largest->size) 62 largest = area; 63 } 64 65 /* If no suitable area was found, return an error. */ 66 assert(largest); 67 if (!largest || largest->size < (2 << 20)) 68 panic("No available memory found for relocation"); 69 70 dest_addr = largest->start + largest->size; 71 72 return (ulong)dest_addr; 73 } 74 75 void dram_init_banksize(void) 76 { 77 struct memory_info *info = &gd->arch.meminfo; 78 int num_banks; 79 int i; 80 81 for (i = 0, num_banks = 0; i < info->num_areas; i++) { 82 struct memory_area *area = &info->area[i]; 83 84 if (area->start >= 1ULL << 32) 85 continue; 86 gd->bd->bi_dram[num_banks].start = area->start; 87 gd->bd->bi_dram[num_banks].size = area->size; 88 num_banks++; 89 } 90 } 91 92 static int read_seed_from_cmos(struct pei_data *pei_data) 93 { 94 u16 c1, c2, checksum, seed_checksum; 95 struct udevice *dev; 96 int ret = 0; 97 98 ret = uclass_get_device(UCLASS_RTC, 0, &dev); 99 if (ret) { 100 debug("Cannot find RTC: err=%d\n", ret); 101 return -ENODEV; 102 } 103 104 /* 105 * Read scrambler seeds from CMOS RAM. We don't want to store them in 106 * SPI flash since they change on every boot and that would wear down 107 * the flash too much. So we store these in CMOS and the large MRC 108 * data in SPI flash. 109 */ 110 ret = rtc_read32(dev, CMOS_OFFSET_MRC_SEED, &pei_data->scrambler_seed); 111 if (!ret) { 112 ret = rtc_read32(dev, CMOS_OFFSET_MRC_SEED_S3, 113 &pei_data->scrambler_seed_s3); 114 } 115 if (ret) { 116 debug("Failed to read from RTC %s\n", dev->name); 117 return ret; 118 } 119 120 debug("Read scrambler seed 0x%08x from CMOS 0x%02x\n", 121 pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); 122 debug("Read S3 scrambler seed 0x%08x from CMOS 0x%02x\n", 123 pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); 124 125 /* Compute seed checksum and compare */ 126 c1 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed, 127 sizeof(u32)); 128 c2 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed_s3, 129 sizeof(u32)); 130 checksum = add_ip_checksums(sizeof(u32), c1, c2); 131 132 seed_checksum = rtc_read8(dev, CMOS_OFFSET_MRC_SEED_CHK); 133 seed_checksum |= rtc_read8(dev, CMOS_OFFSET_MRC_SEED_CHK + 1) << 8; 134 135 if (checksum != seed_checksum) { 136 debug("%s: invalid seed checksum\n", __func__); 137 pei_data->scrambler_seed = 0; 138 pei_data->scrambler_seed_s3 = 0; 139 return -EINVAL; 140 } 141 142 return 0; 143 } 144 145 static int prepare_mrc_cache(struct pei_data *pei_data) 146 { 147 struct mrc_data_container *mrc_cache; 148 struct mrc_region entry; 149 int ret; 150 151 ret = read_seed_from_cmos(pei_data); 152 if (ret) 153 return ret; 154 ret = mrccache_get_region(NULL, &entry); 155 if (ret) 156 return ret; 157 mrc_cache = mrccache_find_current(&entry); 158 if (!mrc_cache) 159 return -ENOENT; 160 161 pei_data->mrc_input = mrc_cache->data; 162 pei_data->mrc_input_len = mrc_cache->data_size; 163 debug("%s: at %p, size %x checksum %04x\n", __func__, 164 pei_data->mrc_input, pei_data->mrc_input_len, 165 mrc_cache->checksum); 166 167 return 0; 168 } 169 170 static int write_seeds_to_cmos(struct pei_data *pei_data) 171 { 172 u16 c1, c2, checksum; 173 struct udevice *dev; 174 int ret = 0; 175 176 ret = uclass_get_device(UCLASS_RTC, 0, &dev); 177 if (ret) { 178 debug("Cannot find RTC: err=%d\n", ret); 179 return -ENODEV; 180 } 181 182 /* Save the MRC seed values to CMOS */ 183 rtc_write32(dev, CMOS_OFFSET_MRC_SEED, pei_data->scrambler_seed); 184 debug("Save scrambler seed 0x%08x to CMOS 0x%02x\n", 185 pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); 186 187 rtc_write32(dev, CMOS_OFFSET_MRC_SEED_S3, pei_data->scrambler_seed_s3); 188 debug("Save s3 scrambler seed 0x%08x to CMOS 0x%02x\n", 189 pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); 190 191 /* Save a simple checksum of the seed values */ 192 c1 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed, 193 sizeof(u32)); 194 c2 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed_s3, 195 sizeof(u32)); 196 checksum = add_ip_checksums(sizeof(u32), c1, c2); 197 198 rtc_write8(dev, CMOS_OFFSET_MRC_SEED_CHK, checksum & 0xff); 199 rtc_write8(dev, CMOS_OFFSET_MRC_SEED_CHK + 1, (checksum >> 8) & 0xff); 200 201 return 0; 202 } 203 204 /* Use this hook to save our SDRAM parameters */ 205 int misc_init_r(void) 206 { 207 int ret; 208 209 ret = mrccache_save(); 210 if (ret) 211 printf("Unable to save MRC data: %d\n", ret); 212 213 return 0; 214 } 215 216 static const char *const ecc_decoder[] = { 217 "inactive", 218 "active on IO", 219 "disabled on IO", 220 "active" 221 }; 222 223 /* 224 * Dump in the log memory controller configuration as read from the memory 225 * controller registers. 226 */ 227 static void report_memory_config(void) 228 { 229 u32 addr_decoder_common, addr_decode_ch[2]; 230 int i; 231 232 addr_decoder_common = readl(MCHBAR_REG(0x5000)); 233 addr_decode_ch[0] = readl(MCHBAR_REG(0x5004)); 234 addr_decode_ch[1] = readl(MCHBAR_REG(0x5008)); 235 236 debug("memcfg DDR3 clock %d MHz\n", 237 (readl(MCHBAR_REG(0x5e04)) * 13333 * 2 + 50) / 100); 238 debug("memcfg channel assignment: A: %d, B % d, C % d\n", 239 addr_decoder_common & 3, 240 (addr_decoder_common >> 2) & 3, 241 (addr_decoder_common >> 4) & 3); 242 243 for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { 244 u32 ch_conf = addr_decode_ch[i]; 245 debug("memcfg channel[%d] config (%8.8x):\n", i, ch_conf); 246 debug(" ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]); 247 debug(" enhanced interleave mode %s\n", 248 ((ch_conf >> 22) & 1) ? "on" : "off"); 249 debug(" rank interleave %s\n", 250 ((ch_conf >> 21) & 1) ? "on" : "off"); 251 debug(" DIMMA %d MB width x%d %s rank%s\n", 252 ((ch_conf >> 0) & 0xff) * 256, 253 ((ch_conf >> 19) & 1) ? 16 : 8, 254 ((ch_conf >> 17) & 1) ? "dual" : "single", 255 ((ch_conf >> 16) & 1) ? "" : ", selected"); 256 debug(" DIMMB %d MB width x%d %s rank%s\n", 257 ((ch_conf >> 8) & 0xff) * 256, 258 ((ch_conf >> 20) & 1) ? 16 : 8, 259 ((ch_conf >> 18) & 1) ? "dual" : "single", 260 ((ch_conf >> 16) & 1) ? ", selected" : ""); 261 } 262 } 263 264 static void post_system_agent_init(struct pei_data *pei_data) 265 { 266 /* If PCIe init is skipped, set the PEG clock gating */ 267 if (!pei_data->pcie_init) 268 setbits_le32(MCHBAR_REG(0x7010), 1); 269 } 270 271 static asmlinkage void console_tx_byte(unsigned char byte) 272 { 273 #ifdef DEBUG 274 putc(byte); 275 #endif 276 } 277 278 static int recovery_mode_enabled(void) 279 { 280 return false; 281 } 282 283 /** 284 * Find the PEI executable in the ROM and execute it. 285 * 286 * @param pei_data: configuration data for UEFI PEI reference code 287 */ 288 int sdram_initialise(struct pei_data *pei_data) 289 { 290 unsigned version; 291 const char *data; 292 uint16_t done; 293 int ret; 294 295 report_platform_info(); 296 297 /* Wait for ME to be ready */ 298 ret = intel_early_me_init(); 299 if (ret) 300 return ret; 301 ret = intel_early_me_uma_size(); 302 if (ret < 0) 303 return ret; 304 305 debug("Starting UEFI PEI System Agent\n"); 306 307 /* 308 * Do not pass MRC data in for recovery mode boot, 309 * Always pass it in for S3 resume. 310 */ 311 if (!recovery_mode_enabled() || 312 pei_data->boot_mode == PEI_BOOT_RESUME) { 313 ret = prepare_mrc_cache(pei_data); 314 if (ret) 315 debug("prepare_mrc_cache failed: %d\n", ret); 316 } 317 318 /* If MRC data is not found we cannot continue S3 resume. */ 319 if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) { 320 debug("Giving up in sdram_initialize: No MRC data\n"); 321 reset_cpu(0); 322 } 323 324 /* Pass console handler in pei_data */ 325 pei_data->tx_byte = console_tx_byte; 326 327 debug("PEI data at %p, size %x:\n", pei_data, sizeof(*pei_data)); 328 329 data = (char *)CONFIG_X86_MRC_ADDR; 330 if (data) { 331 int rv; 332 int (*func)(struct pei_data *); 333 ulong start; 334 335 debug("Calling MRC at %p\n", data); 336 post_code(POST_PRE_MRC); 337 start = get_timer(0); 338 func = (int (*)(struct pei_data *))data; 339 rv = func(pei_data); 340 post_code(POST_MRC); 341 if (rv) { 342 switch (rv) { 343 case -1: 344 printf("PEI version mismatch.\n"); 345 break; 346 case -2: 347 printf("Invalid memory frequency.\n"); 348 break; 349 default: 350 printf("MRC returned %x.\n", rv); 351 } 352 printf("Nonzero MRC return value.\n"); 353 return -EFAULT; 354 } 355 debug("MRC execution time %lu ms\n", get_timer(start)); 356 } else { 357 printf("UEFI PEI System Agent not found.\n"); 358 return -ENOSYS; 359 } 360 361 #if CONFIG_USBDEBUG 362 /* mrc.bin reconfigures USB, so reinit it to have debug */ 363 early_usbdebug_init(); 364 #endif 365 366 version = readl(MCHBAR_REG(0x5034)); 367 debug("System Agent Version %d.%d.%d Build %d\n", 368 version >> 24 , (version >> 16) & 0xff, 369 (version >> 8) & 0xff, version & 0xff); 370 debug("MRC output data length %#x at %p\n", pei_data->mrc_output_len, 371 pei_data->mrc_output); 372 373 /* 374 * Send ME init done for SandyBridge here. This is done inside the 375 * SystemAgent binary on IvyBridge 376 */ 377 done = x86_pci_read_config32(PCH_DEV, PCI_DEVICE_ID); 378 done &= BASE_REV_MASK; 379 if (BASE_REV_SNB == done) 380 intel_early_me_init_done(ME_INIT_STATUS_SUCCESS); 381 else 382 intel_early_me_status(); 383 384 post_system_agent_init(pei_data); 385 report_memory_config(); 386 387 /* S3 resume: don't save scrambler seed or MRC data */ 388 if (pei_data->boot_mode != PEI_BOOT_RESUME) { 389 /* 390 * This will be copied to SDRAM in reserve_arch(), then written 391 * to SPI flash in mrccache_save() 392 */ 393 gd->arch.mrc_output = (char *)pei_data->mrc_output; 394 gd->arch.mrc_output_len = pei_data->mrc_output_len; 395 ret = write_seeds_to_cmos(pei_data); 396 if (ret) 397 debug("Failed to write seeds to CMOS: %d\n", ret); 398 } 399 400 return 0; 401 } 402 403 int reserve_arch(void) 404 { 405 return mrccache_reserve(); 406 } 407 408 static int copy_spd(struct pei_data *peid) 409 { 410 const int gpio_vector[] = {41, 42, 43, 10, -1}; 411 int spd_index; 412 const void *blob = gd->fdt_blob; 413 int node, spd_node; 414 int ret, i; 415 416 for (i = 0; ; i++) { 417 if (gpio_vector[i] == -1) 418 break; 419 ret = gpio_requestf(gpio_vector[i], "spd_id%d", i); 420 if (ret) { 421 debug("%s: Could not request gpio %d\n", __func__, 422 gpio_vector[i]); 423 return ret; 424 } 425 } 426 spd_index = gpio_get_values_as_int(gpio_vector); 427 debug("spd index %d\n", spd_index); 428 node = fdtdec_next_compatible(blob, 0, COMPAT_MEMORY_SPD); 429 if (node < 0) { 430 printf("SPD data not found.\n"); 431 return -ENOENT; 432 } 433 434 for (spd_node = fdt_first_subnode(blob, node); 435 spd_node > 0; 436 spd_node = fdt_next_subnode(blob, spd_node)) { 437 const char *data; 438 int len; 439 440 if (fdtdec_get_int(blob, spd_node, "reg", -1) != spd_index) 441 continue; 442 data = fdt_getprop(blob, spd_node, "data", &len); 443 if (len < sizeof(peid->spd_data[0])) { 444 printf("Missing SPD data\n"); 445 return -EINVAL; 446 } 447 448 debug("Using SDRAM SPD data for '%s'\n", 449 fdt_get_name(blob, spd_node, NULL)); 450 memcpy(peid->spd_data[0], data, sizeof(peid->spd_data[0])); 451 break; 452 } 453 454 if (spd_node < 0) { 455 printf("No SPD data found for index %d\n", spd_index); 456 return -ENOENT; 457 } 458 459 return 0; 460 } 461 462 /** 463 * add_memory_area() - Add a new usable memory area to our list 464 * 465 * Note: @start and @end must not span the first 4GB boundary 466 * 467 * @info: Place to store memory info 468 * @start: Start of this memory area 469 * @end: End of this memory area + 1 470 */ 471 static int add_memory_area(struct memory_info *info, 472 uint64_t start, uint64_t end) 473 { 474 struct memory_area *ptr; 475 476 if (info->num_areas == CONFIG_NR_DRAM_BANKS) 477 return -ENOSPC; 478 479 ptr = &info->area[info->num_areas]; 480 ptr->start = start; 481 ptr->size = end - start; 482 info->total_memory += ptr->size; 483 if (ptr->start < (1ULL << 32)) 484 info->total_32bit_memory += ptr->size; 485 debug("%d: memory %llx size %llx, total now %llx / %llx\n", 486 info->num_areas, ptr->start, ptr->size, 487 info->total_32bit_memory, info->total_memory); 488 info->num_areas++; 489 490 return 0; 491 } 492 493 /** 494 * sdram_find() - Find available memory 495 * 496 * This is a bit complicated since on x86 there are system memory holes all 497 * over the place. We create a list of available memory blocks 498 */ 499 static int sdram_find(pci_dev_t dev) 500 { 501 struct memory_info *info = &gd->arch.meminfo; 502 uint32_t tseg_base, uma_size, tolud; 503 uint64_t tom, me_base, touud; 504 uint64_t uma_memory_base = 0; 505 uint64_t uma_memory_size; 506 unsigned long long tomk; 507 uint16_t ggc; 508 509 /* Total Memory 2GB example: 510 * 511 * 00000000 0000MB-1992MB 1992MB RAM (writeback) 512 * 7c800000 1992MB-2000MB 8MB TSEG (SMRR) 513 * 7d000000 2000MB-2002MB 2MB GFX GTT (uncached) 514 * 7d200000 2002MB-2034MB 32MB GFX UMA (uncached) 515 * 7f200000 2034MB TOLUD 516 * 7f800000 2040MB MEBASE 517 * 7f800000 2040MB-2048MB 8MB ME UMA (uncached) 518 * 80000000 2048MB TOM 519 * 100000000 4096MB-4102MB 6MB RAM (writeback) 520 * 521 * Total Memory 4GB example: 522 * 523 * 00000000 0000MB-2768MB 2768MB RAM (writeback) 524 * ad000000 2768MB-2776MB 8MB TSEG (SMRR) 525 * ad800000 2776MB-2778MB 2MB GFX GTT (uncached) 526 * ada00000 2778MB-2810MB 32MB GFX UMA (uncached) 527 * afa00000 2810MB TOLUD 528 * ff800000 4088MB MEBASE 529 * ff800000 4088MB-4096MB 8MB ME UMA (uncached) 530 * 100000000 4096MB TOM 531 * 100000000 4096MB-5374MB 1278MB RAM (writeback) 532 * 14fe00000 5368MB TOUUD 533 */ 534 535 /* Top of Upper Usable DRAM, including remap */ 536 touud = x86_pci_read_config32(dev, TOUUD+4); 537 touud <<= 32; 538 touud |= x86_pci_read_config32(dev, TOUUD); 539 540 /* Top of Lower Usable DRAM */ 541 tolud = x86_pci_read_config32(dev, TOLUD); 542 543 /* Top of Memory - does not account for any UMA */ 544 tom = x86_pci_read_config32(dev, 0xa4); 545 tom <<= 32; 546 tom |= x86_pci_read_config32(dev, 0xa0); 547 548 debug("TOUUD %llx TOLUD %08x TOM %llx\n", touud, tolud, tom); 549 550 /* ME UMA needs excluding if total memory <4GB */ 551 me_base = x86_pci_read_config32(dev, 0x74); 552 me_base <<= 32; 553 me_base |= x86_pci_read_config32(dev, 0x70); 554 555 debug("MEBASE %llx\n", me_base); 556 557 /* TODO: Get rid of all this shifting by 10 bits */ 558 tomk = tolud >> 10; 559 if (me_base == tolud) { 560 /* ME is from MEBASE-TOM */ 561 uma_size = (tom - me_base) >> 10; 562 /* Increment TOLUD to account for ME as RAM */ 563 tolud += uma_size << 10; 564 /* UMA starts at old TOLUD */ 565 uma_memory_base = tomk * 1024ULL; 566 uma_memory_size = uma_size * 1024ULL; 567 debug("ME UMA base %llx size %uM\n", me_base, uma_size >> 10); 568 } 569 570 /* Graphics memory comes next */ 571 ggc = x86_pci_read_config16(dev, GGC); 572 if (!(ggc & 2)) { 573 debug("IGD decoded, subtracting "); 574 575 /* Graphics memory */ 576 uma_size = ((ggc >> 3) & 0x1f) * 32 * 1024ULL; 577 debug("%uM UMA", uma_size >> 10); 578 tomk -= uma_size; 579 uma_memory_base = tomk * 1024ULL; 580 uma_memory_size += uma_size * 1024ULL; 581 582 /* GTT Graphics Stolen Memory Size (GGMS) */ 583 uma_size = ((ggc >> 8) & 0x3) * 1024ULL; 584 tomk -= uma_size; 585 uma_memory_base = tomk * 1024ULL; 586 uma_memory_size += uma_size * 1024ULL; 587 debug(" and %uM GTT\n", uma_size >> 10); 588 } 589 590 /* Calculate TSEG size from its base which must be below GTT */ 591 tseg_base = x86_pci_read_config32(dev, 0xb8); 592 uma_size = (uma_memory_base - tseg_base) >> 10; 593 tomk -= uma_size; 594 uma_memory_base = tomk * 1024ULL; 595 uma_memory_size += uma_size * 1024ULL; 596 debug("TSEG base 0x%08x size %uM\n", tseg_base, uma_size >> 10); 597 598 debug("Available memory below 4GB: %lluM\n", tomk >> 10); 599 600 /* Report the memory regions */ 601 add_memory_area(info, 1 << 20, 2 << 28); 602 add_memory_area(info, (2 << 28) + (2 << 20), 4 << 28); 603 add_memory_area(info, (4 << 28) + (2 << 20), tseg_base); 604 add_memory_area(info, 1ULL << 32, touud); 605 606 /* Add MTRRs for memory */ 607 mtrr_add_request(MTRR_TYPE_WRBACK, 0, 2ULL << 30); 608 mtrr_add_request(MTRR_TYPE_WRBACK, 2ULL << 30, 512 << 20); 609 mtrr_add_request(MTRR_TYPE_WRBACK, 0xaULL << 28, 256 << 20); 610 mtrr_add_request(MTRR_TYPE_UNCACHEABLE, tseg_base, 16 << 20); 611 mtrr_add_request(MTRR_TYPE_UNCACHEABLE, tseg_base + (16 << 20), 612 32 << 20); 613 614 /* 615 * If >= 4GB installed then memory from TOLUD to 4GB 616 * is remapped above TOM, TOUUD will account for both 617 */ 618 if (touud > (1ULL << 32ULL)) { 619 debug("Available memory above 4GB: %lluM\n", 620 (touud >> 20) - 4096); 621 } 622 623 return 0; 624 } 625 626 static void rcba_config(void) 627 { 628 /* 629 * GFX INTA -> PIRQA (MSI) 630 * D28IP_P3IP WLAN INTA -> PIRQB 631 * D29IP_E1P EHCI1 INTA -> PIRQD 632 * D26IP_E2P EHCI2 INTA -> PIRQF 633 * D31IP_SIP SATA INTA -> PIRQF (MSI) 634 * D31IP_SMIP SMBUS INTB -> PIRQH 635 * D31IP_TTIP THRT INTC -> PIRQA 636 * D27IP_ZIP HDA INTA -> PIRQA (MSI) 637 * 638 * TRACKPAD -> PIRQE (Edge Triggered) 639 * TOUCHSCREEN -> PIRQG (Edge Triggered) 640 */ 641 642 /* Device interrupt pin register (board specific) */ 643 writel((INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | 644 (INTB << D31IP_SMIP) | (INTA << D31IP_SIP), RCB_REG(D31IP)); 645 writel(NOINT << D30IP_PIP, RCB_REG(D30IP)); 646 writel(INTA << D29IP_E1P, RCB_REG(D29IP)); 647 writel(INTA << D28IP_P3IP, RCB_REG(D28IP)); 648 writel(INTA << D27IP_ZIP, RCB_REG(D27IP)); 649 writel(INTA << D26IP_E2P, RCB_REG(D26IP)); 650 writel(NOINT << D25IP_LIP, RCB_REG(D25IP)); 651 writel(NOINT << D22IP_MEI1IP, RCB_REG(D22IP)); 652 653 /* Device interrupt route registers */ 654 writel(DIR_ROUTE(PIRQB, PIRQH, PIRQA, PIRQC), RCB_REG(D31IR)); 655 writel(DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG), RCB_REG(D29IR)); 656 writel(DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE), RCB_REG(D28IR)); 657 writel(DIR_ROUTE(PIRQA, PIRQH, PIRQA, PIRQB), RCB_REG(D27IR)); 658 writel(DIR_ROUTE(PIRQF, PIRQE, PIRQG, PIRQH), RCB_REG(D26IR)); 659 writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D25IR)); 660 writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D22IR)); 661 662 /* Enable IOAPIC (generic) */ 663 writew(0x0100, RCB_REG(OIC)); 664 /* PCH BWG says to read back the IOAPIC enable register */ 665 (void)readw(RCB_REG(OIC)); 666 667 /* Disable unused devices (board specific) */ 668 setbits_le32(RCB_REG(FD), PCH_DISABLE_ALWAYS); 669 } 670 671 int dram_init(void) 672 { 673 struct pei_data pei_data __aligned(8) = { 674 .pei_version = PEI_VERSION, 675 .mchbar = DEFAULT_MCHBAR, 676 .dmibar = DEFAULT_DMIBAR, 677 .epbar = DEFAULT_EPBAR, 678 .pciexbar = CONFIG_PCIE_ECAM_BASE, 679 .smbusbar = SMBUS_IO_BASE, 680 .wdbbar = 0x4000000, 681 .wdbsize = 0x1000, 682 .hpet_address = CONFIG_HPET_ADDRESS, 683 .rcba = DEFAULT_RCBABASE, 684 .pmbase = DEFAULT_PMBASE, 685 .gpiobase = DEFAULT_GPIOBASE, 686 .thermalbase = 0xfed08000, 687 .system_type = 0, /* 0 Mobile, 1 Desktop/Server */ 688 .tseg_size = CONFIG_SMM_TSEG_SIZE, 689 .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, 690 .ec_present = 1, 691 .ddr3lv_support = 1, 692 /* 693 * 0 = leave channel enabled 694 * 1 = disable dimm 0 on channel 695 * 2 = disable dimm 1 on channel 696 * 3 = disable dimm 0+1 on channel 697 */ 698 .dimm_channel0_disabled = 2, 699 .dimm_channel1_disabled = 2, 700 .max_ddr3_freq = 1600, 701 .usb_port_config = { 702 /* 703 * Empty and onboard Ports 0-7, set to un-used pin 704 * OC3 705 */ 706 { 0, 3, 0x0000 }, /* P0= Empty */ 707 { 1, 0, 0x0040 }, /* P1= Left USB 1 (OC0) */ 708 { 1, 1, 0x0040 }, /* P2= Left USB 2 (OC1) */ 709 { 1, 3, 0x0040 }, /* P3= SDCARD (no OC) */ 710 { 0, 3, 0x0000 }, /* P4= Empty */ 711 { 1, 3, 0x0040 }, /* P5= WWAN (no OC) */ 712 { 0, 3, 0x0000 }, /* P6= Empty */ 713 { 0, 3, 0x0000 }, /* P7= Empty */ 714 /* 715 * Empty and onboard Ports 8-13, set to un-used pin 716 * OC4 717 */ 718 { 1, 4, 0x0040 }, /* P8= Camera (no OC) */ 719 { 1, 4, 0x0040 }, /* P9= Bluetooth (no OC) */ 720 { 0, 4, 0x0000 }, /* P10= Empty */ 721 { 0, 4, 0x0000 }, /* P11= Empty */ 722 { 0, 4, 0x0000 }, /* P12= Empty */ 723 { 0, 4, 0x0000 }, /* P13= Empty */ 724 }, 725 }; 726 pci_dev_t dev = PCI_BDF(0, 0, 0); 727 int ret; 728 729 debug("Boot mode %d\n", gd->arch.pei_boot_mode); 730 debug("mrc_input %p\n", pei_data.mrc_input); 731 pei_data.boot_mode = gd->arch.pei_boot_mode; 732 ret = copy_spd(&pei_data); 733 if (!ret) 734 ret = sdram_initialise(&pei_data); 735 if (ret) 736 return ret; 737 738 rcba_config(); 739 quick_ram_check(); 740 741 writew(0xCAFE, MCHBAR_REG(SSKPD)); 742 743 post_code(POST_DRAM); 744 745 ret = sdram_find(dev); 746 if (ret) 747 return ret; 748 749 gd->ram_size = gd->arch.meminfo.total_32bit_memory; 750 751 return 0; 752 } 753