1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2011 The Chromium OS Authors. 4 * (C) Copyright 2010,2011 5 * Graeme Russ, <graeme.russ@gmail.com> 6 * 7 * Portions from Coreboot mainboard/google/link/romstage.c 8 * Copyright (C) 2007-2010 coresystems GmbH 9 * Copyright (C) 2011 Google Inc. 10 */ 11 12 #include <common.h> 13 #include <errno.h> 14 #include <fdtdec.h> 15 #include <malloc.h> 16 #include <net.h> 17 #include <rtc.h> 18 #include <spi.h> 19 #include <spi_flash.h> 20 #include <syscon.h> 21 #include <asm/cpu.h> 22 #include <asm/processor.h> 23 #include <asm/gpio.h> 24 #include <asm/global_data.h> 25 #include <asm/intel_regs.h> 26 #include <asm/mrccache.h> 27 #include <asm/mrc_common.h> 28 #include <asm/mtrr.h> 29 #include <asm/pci.h> 30 #include <asm/report_platform.h> 31 #include <asm/arch/me.h> 32 #include <asm/arch/pei_data.h> 33 #include <asm/arch/pch.h> 34 #include <asm/post.h> 35 #include <asm/arch/sandybridge.h> 36 37 DECLARE_GLOBAL_DATA_PTR; 38 39 #define CMOS_OFFSET_MRC_SEED 152 40 #define CMOS_OFFSET_MRC_SEED_S3 156 41 #define CMOS_OFFSET_MRC_SEED_CHK 160 42 43 ulong board_get_usable_ram_top(ulong total_size) 44 { 45 return mrc_common_board_get_usable_ram_top(total_size); 46 } 47 48 int dram_init_banksize(void) 49 { 50 mrc_common_dram_init_banksize(); 51 52 return 0; 53 } 54 55 static int read_seed_from_cmos(struct pei_data *pei_data) 56 { 57 u16 c1, c2, checksum, seed_checksum; 58 struct udevice *dev; 59 int ret = 0; 60 61 ret = uclass_get_device(UCLASS_RTC, 0, &dev); 62 if (ret) { 63 debug("Cannot find RTC: err=%d\n", ret); 64 return -ENODEV; 65 } 66 67 /* 68 * Read scrambler seeds from CMOS RAM. We don't want to store them in 69 * SPI flash since they change on every boot and that would wear down 70 * the flash too much. So we store these in CMOS and the large MRC 71 * data in SPI flash. 72 */ 73 ret = rtc_read32(dev, CMOS_OFFSET_MRC_SEED, &pei_data->scrambler_seed); 74 if (!ret) { 75 ret = rtc_read32(dev, CMOS_OFFSET_MRC_SEED_S3, 76 &pei_data->scrambler_seed_s3); 77 } 78 if (ret) { 79 debug("Failed to read from RTC %s\n", dev->name); 80 return ret; 81 } 82 83 debug("Read scrambler seed 0x%08x from CMOS 0x%02x\n", 84 pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); 85 debug("Read S3 scrambler seed 0x%08x from CMOS 0x%02x\n", 86 pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); 87 88 /* Compute seed checksum and compare */ 89 c1 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed, 90 sizeof(u32)); 91 c2 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed_s3, 92 sizeof(u32)); 93 checksum = add_ip_checksums(sizeof(u32), c1, c2); 94 95 seed_checksum = rtc_read8(dev, CMOS_OFFSET_MRC_SEED_CHK); 96 seed_checksum |= rtc_read8(dev, CMOS_OFFSET_MRC_SEED_CHK + 1) << 8; 97 98 if (checksum != seed_checksum) { 99 debug("%s: invalid seed checksum\n", __func__); 100 pei_data->scrambler_seed = 0; 101 pei_data->scrambler_seed_s3 = 0; 102 return -EINVAL; 103 } 104 105 return 0; 106 } 107 108 static int prepare_mrc_cache(struct pei_data *pei_data) 109 { 110 struct mrc_data_container *mrc_cache; 111 struct mrc_region entry; 112 int ret; 113 114 ret = read_seed_from_cmos(pei_data); 115 if (ret) 116 return ret; 117 ret = mrccache_get_region(NULL, &entry); 118 if (ret) 119 return ret; 120 mrc_cache = mrccache_find_current(&entry); 121 if (!mrc_cache) 122 return -ENOENT; 123 124 pei_data->mrc_input = mrc_cache->data; 125 pei_data->mrc_input_len = mrc_cache->data_size; 126 debug("%s: at %p, size %x checksum %04x\n", __func__, 127 pei_data->mrc_input, pei_data->mrc_input_len, 128 mrc_cache->checksum); 129 130 return 0; 131 } 132 133 static int write_seeds_to_cmos(struct pei_data *pei_data) 134 { 135 u16 c1, c2, checksum; 136 struct udevice *dev; 137 int ret = 0; 138 139 ret = uclass_get_device(UCLASS_RTC, 0, &dev); 140 if (ret) { 141 debug("Cannot find RTC: err=%d\n", ret); 142 return -ENODEV; 143 } 144 145 /* Save the MRC seed values to CMOS */ 146 rtc_write32(dev, CMOS_OFFSET_MRC_SEED, pei_data->scrambler_seed); 147 debug("Save scrambler seed 0x%08x to CMOS 0x%02x\n", 148 pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); 149 150 rtc_write32(dev, CMOS_OFFSET_MRC_SEED_S3, pei_data->scrambler_seed_s3); 151 debug("Save s3 scrambler seed 0x%08x to CMOS 0x%02x\n", 152 pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); 153 154 /* Save a simple checksum of the seed values */ 155 c1 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed, 156 sizeof(u32)); 157 c2 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed_s3, 158 sizeof(u32)); 159 checksum = add_ip_checksums(sizeof(u32), c1, c2); 160 161 rtc_write8(dev, CMOS_OFFSET_MRC_SEED_CHK, checksum & 0xff); 162 rtc_write8(dev, CMOS_OFFSET_MRC_SEED_CHK + 1, (checksum >> 8) & 0xff); 163 164 return 0; 165 } 166 167 /* Use this hook to save our SDRAM parameters */ 168 int misc_init_r(void) 169 { 170 int ret; 171 172 ret = mrccache_save(); 173 if (ret) 174 printf("Unable to save MRC data: %d\n", ret); 175 176 return 0; 177 } 178 179 static void post_system_agent_init(struct udevice *dev, struct udevice *me_dev, 180 struct pei_data *pei_data) 181 { 182 uint16_t done; 183 184 /* 185 * Send ME init done for SandyBridge here. This is done inside the 186 * SystemAgent binary on IvyBridge 187 */ 188 dm_pci_read_config16(dev, PCI_DEVICE_ID, &done); 189 done &= BASE_REV_MASK; 190 if (BASE_REV_SNB == done) 191 intel_early_me_init_done(dev, me_dev, ME_INIT_STATUS_SUCCESS); 192 else 193 intel_me_status(me_dev); 194 195 /* If PCIe init is skipped, set the PEG clock gating */ 196 if (!pei_data->pcie_init) 197 setbits_le32(MCHBAR_REG(0x7010), 1); 198 } 199 200 static int recovery_mode_enabled(void) 201 { 202 return false; 203 } 204 205 static int copy_spd(struct udevice *dev, struct pei_data *peid) 206 { 207 const void *data; 208 int ret; 209 210 ret = mrc_locate_spd(dev, sizeof(peid->spd_data[0]), &data); 211 if (ret) { 212 debug("%s: Could not locate SPD (ret=%d)\n", __func__, ret); 213 return ret; 214 } 215 216 memcpy(peid->spd_data[0], data, sizeof(peid->spd_data[0])); 217 218 return 0; 219 } 220 221 /** 222 * sdram_find() - Find available memory 223 * 224 * This is a bit complicated since on x86 there are system memory holes all 225 * over the place. We create a list of available memory blocks 226 * 227 * @dev: Northbridge device 228 */ 229 static int sdram_find(struct udevice *dev) 230 { 231 struct memory_info *info = &gd->arch.meminfo; 232 uint32_t tseg_base, uma_size, tolud; 233 uint64_t tom, me_base, touud; 234 uint64_t uma_memory_base = 0; 235 unsigned long long tomk; 236 uint16_t ggc; 237 u32 val; 238 239 /* Total Memory 2GB example: 240 * 241 * 00000000 0000MB-1992MB 1992MB RAM (writeback) 242 * 7c800000 1992MB-2000MB 8MB TSEG (SMRR) 243 * 7d000000 2000MB-2002MB 2MB GFX GTT (uncached) 244 * 7d200000 2002MB-2034MB 32MB GFX UMA (uncached) 245 * 7f200000 2034MB TOLUD 246 * 7f800000 2040MB MEBASE 247 * 7f800000 2040MB-2048MB 8MB ME UMA (uncached) 248 * 80000000 2048MB TOM 249 * 100000000 4096MB-4102MB 6MB RAM (writeback) 250 * 251 * Total Memory 4GB example: 252 * 253 * 00000000 0000MB-2768MB 2768MB RAM (writeback) 254 * ad000000 2768MB-2776MB 8MB TSEG (SMRR) 255 * ad800000 2776MB-2778MB 2MB GFX GTT (uncached) 256 * ada00000 2778MB-2810MB 32MB GFX UMA (uncached) 257 * afa00000 2810MB TOLUD 258 * ff800000 4088MB MEBASE 259 * ff800000 4088MB-4096MB 8MB ME UMA (uncached) 260 * 100000000 4096MB TOM 261 * 100000000 4096MB-5374MB 1278MB RAM (writeback) 262 * 14fe00000 5368MB TOUUD 263 */ 264 265 /* Top of Upper Usable DRAM, including remap */ 266 dm_pci_read_config32(dev, TOUUD + 4, &val); 267 touud = (uint64_t)val << 32; 268 dm_pci_read_config32(dev, TOUUD, &val); 269 touud |= val; 270 271 /* Top of Lower Usable DRAM */ 272 dm_pci_read_config32(dev, TOLUD, &tolud); 273 274 /* Top of Memory - does not account for any UMA */ 275 dm_pci_read_config32(dev, 0xa4, &val); 276 tom = (uint64_t)val << 32; 277 dm_pci_read_config32(dev, 0xa0, &val); 278 tom |= val; 279 280 debug("TOUUD %llx TOLUD %08x TOM %llx\n", touud, tolud, tom); 281 282 /* ME UMA needs excluding if total memory <4GB */ 283 dm_pci_read_config32(dev, 0x74, &val); 284 me_base = (uint64_t)val << 32; 285 dm_pci_read_config32(dev, 0x70, &val); 286 me_base |= val; 287 288 debug("MEBASE %llx\n", me_base); 289 290 /* TODO: Get rid of all this shifting by 10 bits */ 291 tomk = tolud >> 10; 292 if (me_base == tolud) { 293 /* ME is from MEBASE-TOM */ 294 uma_size = (tom - me_base) >> 10; 295 /* Increment TOLUD to account for ME as RAM */ 296 tolud += uma_size << 10; 297 /* UMA starts at old TOLUD */ 298 uma_memory_base = tomk * 1024ULL; 299 debug("ME UMA base %llx size %uM\n", me_base, uma_size >> 10); 300 } 301 302 /* Graphics memory comes next */ 303 dm_pci_read_config16(dev, GGC, &ggc); 304 if (!(ggc & 2)) { 305 debug("IGD decoded, subtracting "); 306 307 /* Graphics memory */ 308 uma_size = ((ggc >> 3) & 0x1f) * 32 * 1024ULL; 309 debug("%uM UMA", uma_size >> 10); 310 tomk -= uma_size; 311 uma_memory_base = tomk * 1024ULL; 312 313 /* GTT Graphics Stolen Memory Size (GGMS) */ 314 uma_size = ((ggc >> 8) & 0x3) * 1024ULL; 315 tomk -= uma_size; 316 uma_memory_base = tomk * 1024ULL; 317 debug(" and %uM GTT\n", uma_size >> 10); 318 } 319 320 /* Calculate TSEG size from its base which must be below GTT */ 321 dm_pci_read_config32(dev, 0xb8, &tseg_base); 322 uma_size = (uma_memory_base - tseg_base) >> 10; 323 tomk -= uma_size; 324 uma_memory_base = tomk * 1024ULL; 325 debug("TSEG base 0x%08x size %uM\n", tseg_base, uma_size >> 10); 326 327 debug("Available memory below 4GB: %lluM\n", tomk >> 10); 328 329 /* Report the memory regions */ 330 mrc_add_memory_area(info, 1 << 20, 2 << 28); 331 mrc_add_memory_area(info, (2 << 28) + (2 << 20), 4 << 28); 332 mrc_add_memory_area(info, (4 << 28) + (2 << 20), tseg_base); 333 mrc_add_memory_area(info, 1ULL << 32, touud); 334 335 /* Add MTRRs for memory */ 336 mtrr_add_request(MTRR_TYPE_WRBACK, 0, 2ULL << 30); 337 mtrr_add_request(MTRR_TYPE_WRBACK, 2ULL << 30, 512 << 20); 338 mtrr_add_request(MTRR_TYPE_WRBACK, 0xaULL << 28, 256 << 20); 339 mtrr_add_request(MTRR_TYPE_UNCACHEABLE, tseg_base, 16 << 20); 340 mtrr_add_request(MTRR_TYPE_UNCACHEABLE, tseg_base + (16 << 20), 341 32 << 20); 342 343 /* 344 * If >= 4GB installed then memory from TOLUD to 4GB 345 * is remapped above TOM, TOUUD will account for both 346 */ 347 if (touud > (1ULL << 32ULL)) { 348 debug("Available memory above 4GB: %lluM\n", 349 (touud >> 20) - 4096); 350 } 351 352 return 0; 353 } 354 355 static void rcba_config(void) 356 { 357 /* 358 * GFX INTA -> PIRQA (MSI) 359 * D28IP_P3IP WLAN INTA -> PIRQB 360 * D29IP_E1P EHCI1 INTA -> PIRQD 361 * D26IP_E2P EHCI2 INTA -> PIRQF 362 * D31IP_SIP SATA INTA -> PIRQF (MSI) 363 * D31IP_SMIP SMBUS INTB -> PIRQH 364 * D31IP_TTIP THRT INTC -> PIRQA 365 * D27IP_ZIP HDA INTA -> PIRQA (MSI) 366 * 367 * TRACKPAD -> PIRQE (Edge Triggered) 368 * TOUCHSCREEN -> PIRQG (Edge Triggered) 369 */ 370 371 /* Device interrupt pin register (board specific) */ 372 writel((INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | 373 (INTB << D31IP_SMIP) | (INTA << D31IP_SIP), RCB_REG(D31IP)); 374 writel(NOINT << D30IP_PIP, RCB_REG(D30IP)); 375 writel(INTA << D29IP_E1P, RCB_REG(D29IP)); 376 writel(INTA << D28IP_P3IP, RCB_REG(D28IP)); 377 writel(INTA << D27IP_ZIP, RCB_REG(D27IP)); 378 writel(INTA << D26IP_E2P, RCB_REG(D26IP)); 379 writel(NOINT << D25IP_LIP, RCB_REG(D25IP)); 380 writel(NOINT << D22IP_MEI1IP, RCB_REG(D22IP)); 381 382 /* Device interrupt route registers */ 383 writel(DIR_ROUTE(PIRQB, PIRQH, PIRQA, PIRQC), RCB_REG(D31IR)); 384 writel(DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG), RCB_REG(D29IR)); 385 writel(DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE), RCB_REG(D28IR)); 386 writel(DIR_ROUTE(PIRQA, PIRQH, PIRQA, PIRQB), RCB_REG(D27IR)); 387 writel(DIR_ROUTE(PIRQF, PIRQE, PIRQG, PIRQH), RCB_REG(D26IR)); 388 writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D25IR)); 389 writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D22IR)); 390 391 /* Enable IOAPIC (generic) */ 392 writew(0x0100, RCB_REG(OIC)); 393 /* PCH BWG says to read back the IOAPIC enable register */ 394 (void)readw(RCB_REG(OIC)); 395 396 /* Disable unused devices (board specific) */ 397 setbits_le32(RCB_REG(FD), PCH_DISABLE_ALWAYS); 398 } 399 400 int dram_init(void) 401 { 402 struct pei_data _pei_data __aligned(8) = { 403 .pei_version = PEI_VERSION, 404 .mchbar = MCH_BASE_ADDRESS, 405 .dmibar = DEFAULT_DMIBAR, 406 .epbar = DEFAULT_EPBAR, 407 .pciexbar = CONFIG_PCIE_ECAM_BASE, 408 .smbusbar = SMBUS_IO_BASE, 409 .wdbbar = 0x4000000, 410 .wdbsize = 0x1000, 411 .hpet_address = CONFIG_HPET_ADDRESS, 412 .rcba = DEFAULT_RCBABASE, 413 .pmbase = DEFAULT_PMBASE, 414 .gpiobase = DEFAULT_GPIOBASE, 415 .thermalbase = 0xfed08000, 416 .system_type = 0, /* 0 Mobile, 1 Desktop/Server */ 417 .tseg_size = CONFIG_SMM_TSEG_SIZE, 418 .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, 419 .ec_present = 1, 420 .ddr3lv_support = 1, 421 /* 422 * 0 = leave channel enabled 423 * 1 = disable dimm 0 on channel 424 * 2 = disable dimm 1 on channel 425 * 3 = disable dimm 0+1 on channel 426 */ 427 .dimm_channel0_disabled = 2, 428 .dimm_channel1_disabled = 2, 429 .max_ddr3_freq = 1600, 430 .usb_port_config = { 431 /* 432 * Empty and onboard Ports 0-7, set to un-used pin 433 * OC3 434 */ 435 { 0, 3, 0x0000 }, /* P0= Empty */ 436 { 1, 0, 0x0040 }, /* P1= Left USB 1 (OC0) */ 437 { 1, 1, 0x0040 }, /* P2= Left USB 2 (OC1) */ 438 { 1, 3, 0x0040 }, /* P3= SDCARD (no OC) */ 439 { 0, 3, 0x0000 }, /* P4= Empty */ 440 { 1, 3, 0x0040 }, /* P5= WWAN (no OC) */ 441 { 0, 3, 0x0000 }, /* P6= Empty */ 442 { 0, 3, 0x0000 }, /* P7= Empty */ 443 /* 444 * Empty and onboard Ports 8-13, set to un-used pin 445 * OC4 446 */ 447 { 1, 4, 0x0040 }, /* P8= Camera (no OC) */ 448 { 1, 4, 0x0040 }, /* P9= Bluetooth (no OC) */ 449 { 0, 4, 0x0000 }, /* P10= Empty */ 450 { 0, 4, 0x0000 }, /* P11= Empty */ 451 { 0, 4, 0x0000 }, /* P12= Empty */ 452 { 0, 4, 0x0000 }, /* P13= Empty */ 453 }, 454 }; 455 struct pei_data *pei_data = &_pei_data; 456 struct udevice *dev, *me_dev; 457 int ret; 458 459 /* We need the pinctrl set up early */ 460 ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev); 461 if (ret) { 462 debug("%s: Could not get pinconf (ret=%d)\n", __func__, ret); 463 return ret; 464 } 465 466 ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &dev); 467 if (ret) { 468 debug("%s: Could not get northbridge (ret=%d)\n", __func__, 469 ret); 470 return ret; 471 } 472 ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev); 473 if (ret) { 474 debug("%s: Could not get ME (ret=%d)\n", __func__, ret); 475 return ret; 476 } 477 ret = copy_spd(dev, pei_data); 478 if (ret) { 479 debug("%s: Could not get SPD (ret=%d)\n", __func__, ret); 480 return ret; 481 } 482 pei_data->boot_mode = gd->arch.pei_boot_mode; 483 debug("Boot mode %d\n", gd->arch.pei_boot_mode); 484 debug("mrc_input %p\n", pei_data->mrc_input); 485 486 /* 487 * Do not pass MRC data in for recovery mode boot, 488 * Always pass it in for S3 resume. 489 */ 490 if (!recovery_mode_enabled() || 491 pei_data->boot_mode == PEI_BOOT_RESUME) { 492 ret = prepare_mrc_cache(pei_data); 493 if (ret) 494 debug("prepare_mrc_cache failed: %d\n", ret); 495 } 496 497 /* If MRC data is not found we cannot continue S3 resume. */ 498 if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) { 499 debug("Giving up in sdram_initialize: No MRC data\n"); 500 reset_cpu(0); 501 } 502 503 /* Pass console handler in pei_data */ 504 pei_data->tx_byte = sdram_console_tx_byte; 505 506 /* Wait for ME to be ready */ 507 ret = intel_early_me_init(me_dev); 508 if (ret) { 509 debug("%s: Could not init ME (ret=%d)\n", __func__, ret); 510 return ret; 511 } 512 ret = intel_early_me_uma_size(me_dev); 513 if (ret < 0) { 514 debug("%s: Could not get UMA size (ret=%d)\n", __func__, ret); 515 return ret; 516 } 517 518 ret = mrc_common_init(dev, pei_data, false); 519 if (ret) { 520 debug("%s: mrc_common_init() failed (ret=%d)\n", __func__, ret); 521 return ret; 522 } 523 524 ret = sdram_find(dev); 525 if (ret) { 526 debug("%s: sdram_find() failed (ret=%d)\n", __func__, ret); 527 return ret; 528 } 529 gd->ram_size = gd->arch.meminfo.total_32bit_memory; 530 531 debug("MRC output data length %#x at %p\n", pei_data->mrc_output_len, 532 pei_data->mrc_output); 533 534 post_system_agent_init(dev, me_dev, pei_data); 535 report_memory_config(); 536 537 /* S3 resume: don't save scrambler seed or MRC data */ 538 if (pei_data->boot_mode != PEI_BOOT_RESUME) { 539 /* 540 * This will be copied to SDRAM in reserve_arch(), then written 541 * to SPI flash in mrccache_save() 542 */ 543 gd->arch.mrc_output = (char *)pei_data->mrc_output; 544 gd->arch.mrc_output_len = pei_data->mrc_output_len; 545 ret = write_seeds_to_cmos(pei_data); 546 if (ret) 547 debug("Failed to write seeds to CMOS: %d\n", ret); 548 } 549 550 writew(0xCAFE, MCHBAR_REG(SSKPD)); 551 if (ret) 552 return ret; 553 554 rcba_config(); 555 556 return 0; 557 } 558